diff options
author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-09 15:37:09 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:09:09 +0000 |
commit | 2adb50d32e8cd9c61773b1d60de545255c6a4049 (patch) | |
tree | 0c78815666d0b53bf54130e9752690ba29e61c08 /src/soc/intel | |
parent | a54bfd5e950ef108e9941a8319d0c24d786528ec (diff) | |
download | coreboot-2adb50d32e8cd9c61773b1d60de545255c6a4049.tar.xz |
apollolake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Apollo Lake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on octopus system
Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r-- | src/soc/intel/apollolake/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/apollolake/chip.c | 78 | ||||
-rw-r--r-- | src/soc/intel/apollolake/chip.h | 9 | ||||
-rw-r--r-- | src/soc/intel/apollolake/include/soc/msr.h | 9 |
4 files changed, 23 insertions, 74 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 9118b18af8..9323aed8ff 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -61,6 +61,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 058222ce39..cc190bae24 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -15,6 +15,7 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/msr.h> #include <intelblocks/p2sb.h> +#include <intelblocks/power_limit.h> #include <intelblocks/xdci.h> #include <fsp/api.h> #include <fsp/util.h> @@ -34,6 +35,7 @@ #include <spi-generic.h> #include <timer.h> #include <soc/ramstage.h> +#include <soc/soc_chip.h> #include "chip.h" @@ -269,73 +271,6 @@ static void pcie_override_devicetree_after_silicon_init(void) pcie_update_device_tree(PCH_DEVFN_PCIE5, 2); } -/* Configure package power limits */ -static void set_power_limits(void) -{ - struct soc_intel_apollolake_config *cfg; - msr_t rapl_msr_reg, limit; - uint32_t power_unit; - uint32_t tdp, min_power, max_power; - uint32_t pl2_val; - - cfg = config_of_soc(); - - if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { - printk(BIOS_INFO, "Skip the RAPL settings.\n"); - return; - } - - /* Get units */ - rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 1 << (rapl_msr_reg.lo & 0xf); - - /* Get power defaults for this SKU */ - rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU); - tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; - pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; - min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; - max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; - - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - - /* Set PL1 override value */ - tdp = (cfg->tdp_pl1_override_mw == 0) ? - tdp : (cfg->tdp_pl1_override_mw * power_unit) / 1000; - /* Set PL2 override value */ - pl2_val = (cfg->tdp_pl2_override_mw == 0) ? - pl2_val : (cfg->tdp_pl2_override_mw * power_unit) / 1000; - - /* Set long term power limit to TDP */ - limit.lo = tdp & PKG_POWER_LIMIT_MASK; - /* Set PL1 Pkg Power clamp bit */ - limit.lo |= PKG_POWER_LIMIT_CLAMP; - - limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & - PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; - - /* Set short term power limit PL2 */ - limit.hi = pl2_val & PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_EN; - - /* Program package power limits in RAPL MSR */ - wrmsr(MSR_PKG_POWER_LIMIT, limit); - printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit, - 100 * (tdp % power_unit) / power_unit); - printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit, - 100 * (pl2_val % power_unit) / power_unit); - - /* Setting RAPL MMIO register for Power limits. - * RAPL driver is using MSR instead of MMIO. - * So, disabled LIMIT_EN bit for MMIO. */ - MCHBAR32(MCHBAR_RAPL_PPL) = limit.lo & ~PKG_POWER_LIMIT_EN; - MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~PKG_POWER_LIMIT_EN; -} - /* Overwrites the SCI IRQ if another IRQ number is given by device tree. */ static void set_sci_irq(void) { @@ -355,6 +290,9 @@ static void set_sci_irq(void) static void soc_init(void *data) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Snapshot the current GPIO IRQ polarities. FSP is setting a * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); @@ -384,8 +322,10 @@ static void soc_init(void *data) /* Allocate ACPI NVS in CBMEM */ cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t)); - /* Set RAPL MSR for Package power limits*/ - set_power_limits(); + config = config_of_soc(); + /* Set RAPL MSR for Package power limits */ + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); /* * FSP-S routes SCI to IRQ 9. With the help of this function you can diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 8c0a6d2d1a..ce446a063a 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -9,6 +9,7 @@ #include <soc/gpe.h> #include <soc/gpio.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/power_limit.h> #include <device/i2c_simple.h> #include <drivers/i2c/designware/dw_i2c.h> #include <soc/pm.h> @@ -28,6 +29,9 @@ struct soc_intel_apollolake_config { /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Common struct containing power limits configuration info */ + struct soc_power_limits_config power_limits_config; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an @@ -99,11 +103,6 @@ struct soc_intel_apollolake_config { /* TCC activation offset value in degrees Celsius */ int tcc_offset; - /* PL1 override value in mW for APL */ - uint16_t tdp_pl1_override_mw; - /* PL2 override value in mW for APL */ - uint16_t tdp_pl2_override_mw; - /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] */ diff --git a/src/soc/intel/apollolake/include/soc/msr.h b/src/soc/intel/apollolake/include/soc/msr.h new file mode 100644 index 0000000000..cee11c29a8 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/msr.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ + +#include <intelblocks/msr.h> + +#endif |