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authorli feng <li1.feng@intel.com>2020-03-12 16:09:53 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-16 14:46:31 +0000
commit2cf9d3883cc09aa2410135b87d715f47608ae38d (patch)
treeb7aff1e00851ff70f058ecdb316ceb074c2c7b88 /src/soc/intel
parentb159d443dd6e2bd977d30b3cb5db86b38430c1ea (diff)
downloadcoreboot-2cf9d3883cc09aa2410135b87d715f47608ae38d.tar.xz
soc/intel/tigerlake: Support ISH
Add ACPI Object for ISH SSDT Enable/disable ISH based on devicetree BRANCH=none BUG=b:145946347 TEST=boot to OS with TGL RVP UP3 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/tigerlake/acpi/ish.asl22
-rw-r--r--src/soc/intel/tigerlake/acpi/southbridge.asl3
-rw-r--r--src/soc/intel/tigerlake/chip.c1
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_tgl.c7
4 files changed, 33 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/acpi/ish.asl b/src/soc/intel/tigerlake/acpi/ish.asl
new file mode 100644
index 0000000000..186a147f44
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/ish.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Integrated Sensor Hub Controller 0:12.0 */
+
+Device (ISHB)
+{
+ Name (_ADR, 0x00120000)
+ Name (_DDN, "Integrated Sensor Hub Controller")
+}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 9d25a735f5..1403eb4b13 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -49,6 +49,9 @@
/* SMBus 0:1f.4 */
#include "smbus.asl"
+/* ISH 0:12.0 */
+#include "ish.asl"
+
/* USB XHCI 0:14.0 */
#include "xhci.asl"
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index 6f6e153ca6..dc36da34c4 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -71,6 +71,7 @@ const char *soc_acpi_name(const struct device *dev)
switch (dev->path.pci.devfn) {
case SA_DEVFN_ROOT: return "MCHC";
+ case PCH_DEVFN_ISH: return "ISHB";
case PCH_DEVFN_XHCI: return "XHCI";
case PCH_DEVFN_I2C0: return "I2C0";
case PCH_DEVFN_I2C1: return "I2C1";
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index c5629a51c6..b46f3a3f10 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -89,6 +89,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
else
m_cfg->InternalGfx = 0x1;
+ /* ISH */
+ dev = pcidev_path_on_root(PCH_DEVFN_ISH);
+ if (!dev || !dev->enabled)
+ m_cfg->PchIshEnable = 0;
+ else
+ m_cfg->PchIshEnable = 1;
+
/* DP port config */
m_cfg->DdiPortAConfig = config->DdiPortAConfig;
m_cfg->DdiPortBConfig = config->DdiPortBConfig;