diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2016-08-10 11:33:56 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-08-11 22:43:53 +0200 |
| commit | 3a21d0f341104dbef041f1dde8541d6054eb04e6 (patch) | |
| tree | a0b56ec69c4cc9913ffeb231933329a34079a46f /src/soc/intel | |
| parent | 105828d12a36fa0cbb1a5025891722f1c0546ae8 (diff) | |
| download | coreboot-3a21d0f341104dbef041f1dde8541d6054eb04e6.tar.xz | |
soc/apollolake: enable access to RTC NVRAM
FSP unconditionally locks parts of the NVRAM in the RTC.
This change will enable coreboot to update the locking policy
and be able to unlock the region
BUG=chrome-os-partner:55944
TEST=Check 'crossystem dev_boot_usb=1'
Change-Id: I70fd2bafa6ff9eb9cdf284b9780e4b90dee0f4ce
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16144
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 345d7c4446..1b109d0c93 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -397,6 +397,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0; + + /* Disable FSP from locking access to the RTC NVRAM */ + silconfig->RtcLock = 0; } struct chip_operations soc_intel_apollolake_ops = { |