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authorSubrata Banik <subrata.banik@intel.com>2020-09-28 17:50:00 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-10-03 06:57:51 +0000
commit3e959d8e2a05a50ca16430dcacfd4794db1e49fc (patch)
tree6c5bb300d054947906bde2351f345fe134238329 /src/soc/intel
parent8971ccd576a7b0edbd02101b0c3bc3541cb6a741 (diff)
downloadcoreboot-3e959d8e2a05a50ca16430dcacfd4794db1e49fc.tar.xz
soc/intel/common/block/pmc: Add PMC API for low power programming
List of changes: 1. Create Kconfig to select pmc low power program by SoC 2. Add API to make ACPI timer disable 3. Add API to ignore XTAL shutdown for SLP_S0# assertion Change-Id: I017ddc772f02ccba889d316319ab3d5626b80ba5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45794 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/pmclib.h6
-rw-r--r--src/soc/intel/common/block/pmc/Kconfig6
-rw-r--r--src/soc/intel/common/block/pmc/pmclib.c16
3 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index a339fb1e02..fa063f293e 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -229,4 +229,10 @@ void pmc_set_power_failure_state(bool target_on);
uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert,
uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur);
+/* Disabling ACPI PM timer to ensure switches off TCO and necessary of XTAL OSC shutdown */
+void pmc_disable_acpi_timer(void);
+
+/* Disable XTAL shutdown qualification for low power idle. */
+void pmc_ignore_xtal_shutdown(void);
+
#endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */
diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig
index 3aa0da8b1e..ce41b23620 100644
--- a/src/soc/intel/common/block/pmc/Kconfig
+++ b/src/soc/intel/common/block/pmc/Kconfig
@@ -29,3 +29,9 @@ config PMC_GLOBAL_RESET_ENABLE_LOCK
and lock register is located under PMC BASE at offset ETR.
Note that the reset register is still at 0xCF9 this only
controls the enable and lock feature.
+
+config PMC_LOW_POWER_MODE_PROGRAM
+ bool
+ help
+ Enable this for PMC devices to perform registers programming
+ to ensure low power in active idle scenario.
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index ad9c4fec3d..8825bbe441 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -700,3 +700,19 @@ uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert,
return PCH_PM_PWR_CYC_DUR;
}
+
+#if CONFIG(PMC_LOW_POWER_MODE_PROGRAM)
+void pmc_disable_acpi_timer(void)
+{
+ uint8_t *pmcbase = pmc_mmio_regs();
+
+ setbits8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
+}
+
+void pmc_ignore_xtal_shutdown(void)
+{
+ uint8_t *pmcbase = pmc_mmio_regs();
+
+ setbits8(pmcbase + CPPMVRIC, XTALSDQDIS);
+}
+#endif /* PMC_LOW_POWER_MODE_PROGRAM */