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authorMario Scheithauer <mario.scheithauer@siemens.com>2018-08-22 13:03:55 +0200
committerMartin Roth <martinroth@google.com>2018-08-28 14:18:40 +0000
commit403458e7ec0fae1345cd82128b71d5ab0b66fd77 (patch)
tree43de83e3208afbb6c7feb16aba7d203a127dedeb /src/soc/intel
parent24ad29e83c3b5d46c7ba458a504f63eb034837c7 (diff)
downloadcoreboot-403458e7ec0fae1345cd82128b71d5ab0b66fd77.tar.xz
siemens/mc_apl1: Extend circuit life by clock gating and power gating
The firmware of devices connected to LPC should deassert the LPC CLKRUN# signal when there is no bus activity on LPC. Necessary changes: - Enable LPC CLKRUN# - Enable LPC PCE (Power Control Enable) - Enable LPC CCE (Clock Control Enable) - Remove I/O decoding range on LPC for COM 3 - Disable I/O UART driver Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/include/soc/pcr_ids.h2
-rw-r--r--src/soc/intel/common/block/include/intelblocks/lpc_lib.h6
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h
index f8166932db..f6c990e495 100644
--- a/src/soc/intel/apollolake/include/soc/pcr_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright 2017 Intel Corporation.
+ * Copyright (C) 2018 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -31,6 +32,7 @@
#define PID_GPIO_N 0xC5
#define PID_ITSS 0xD0
#define PID_RTC 0xD1
+#define PID_LPC 0xD2
#define PID_AUNIT 0x4d
#define PID_BUNIT 0x4c
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index ba4f045c34..e7b844fc4a 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2017-2018 Intel Corp.
+ * Copyright (C) 2018 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -47,6 +48,11 @@
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
+/* LPC PCR configuration */
+#define PCR_LPC_PRC 0x341c
+#define PCR_LPC_CCE_EN 0xf
+#define PCR_LPC_PCE_EN (9 << 8)
+
/* Serial IRQ control. SERIRQ_QUIET is the default (0). */
enum serirq_mode {
SERIRQ_QUIET,