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| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2016-08-24 20:50:54 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-15 01:15:27 +0200 |
| commit | 5ff7390fcd74fe1cd94d2507cf7c04b1c1eff620 (patch) | |
| tree | 88ed9f3dc2f5f00aca84af5773debfabd3166120 /src/soc/intel | |
| parent | 5bf42c6c23b462d9292e6854d3f334cf17e42825 (diff) | |
| download | coreboot-5ff7390fcd74fe1cd94d2507cf7c04b1c1eff620.tar.xz | |
kunimitsu: Add FSP 2.0 support in romstage
Populate mainboard related Memory Init Params i.e, SPD
Rcomp values, DQ and DQs values.
Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16316
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions