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| author | Philipp Hug <philipp@hug.cx> | 2018-07-07 21:34:31 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-09-13 15:32:53 +0000 |
| commit | 7524400242be26610df143b5d1d781f875239c45 (patch) | |
| tree | a8055581b7f492e2bddbb8937f7649c043db33bd /src/soc/intel | |
| parent | 3e51d530645059093e6dd27c4bbfafb8a216cd41 (diff) | |
| download | coreboot-7524400242be26610df143b5d1d781f875239c45.tar.xz | |
uart/sifive: make divisor configurable
The SiFive UART on the HiFive Unleashed uses the tlclk as input clock
which runs at coreclk / 2.
The input frequency is configured in the board code depending on the
current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz)
Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions