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authorAaron Durbin <adurbin@chromium.org>2014-01-09 10:44:06 -0600
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-13 16:11:40 +0200
commit766482d320e5ec861e72fdb933d73bdfa72c1fb4 (patch)
tree33aa42ffc8baa173f63c07a0eb13063e577a9779 /src/soc/intel
parent19edc3a2e53eb54994a99ca8a868480badcbf227 (diff)
downloadcoreboot-766482d320e5ec861e72fdb933d73bdfa72c1fb4.tar.xz
baytrail: don't SMI on tco timer firing
The SMI on TCO timer timeout policy was copied from other chipsets. However, it's not very advantageous to have the TCO timer timeout trigger an SMI unless the firmware was the one responsible for setting up the timer. BUG=chromium:321832 BRANCH=rambi,squawks TEST=Manually enabled TCO timer. TCO fires and logged in eventlog. Change-Id: I420b14d6aa778335a925784a64160fa885cba20f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181985 Reviewed-on: http://review.coreboot.org/5035 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/baytrail/smm.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index 1fb35d7616..d4b3d58350 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -102,14 +102,14 @@ void southcluster_smm_enable_smi(void)
southcluster_smm_route_gpios();
/* Enable SMI generation:
- * - on TCO events
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
* No SMIs:
+ * - on TCO events
* - on microcontroller writes (io 0x62/0x66)
*/
- enable_smi(TCO_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+ enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)