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authorUsha P <usha.p@intel.com>2020-02-04 11:24:25 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-02-15 04:09:21 +0000
commit77eaecf06b238157decfe19fea02eadfa71a9436 (patch)
tree6da61dbbd0728bc2305ac0a7d08ba0c1b4fb99fc /src/soc/intel
parent611ec48c1db12bad4cbe5bbfde2eb116887971d0 (diff)
downloadcoreboot-77eaecf06b238157decfe19fea02eadfa71a9436.tar.xz
soc/intel/tigerlake: Update PMC Register Base and platform check for JSP
Change: 1. PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP to 0X0A00 for JSP 2. Platform check in espi.c BUG=None TEST= 1. Test for JSL RVP Boot 2. Verify PMC register values are valid for GEN_PMCON and GBLRST_CAUSE from the coreboot console logs. Change-Id: I6017a9703764b5454e7be479c1e08afe614908f1 Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38704 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c2
-rw-r--r--src/soc/intel/tigerlake/espi.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 1654809a6b..cd264d682c 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -41,7 +41,7 @@
#include <soc/pm.h>
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x1100
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0x0980
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0xA00
#define PCR_PSFX_TO_SHDW_BAR0 0
#define PCR_PSFX_TO_SHDW_BAR1 0x4
#define PCR_PSFX_TO_SHDW_BAR2 0x8
diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c
index d07a582a32..7efd210cad 100644
--- a/src/soc/intel/tigerlake/espi.c
+++ b/src/soc/intel/tigerlake/espi.c
@@ -83,7 +83,7 @@ uint8_t get_pch_series(void)
if (lpc_did_hi_byte == 0xA0)
return PCH_TGP;
- else if (lpc_did_hi_byte == 0x38)
+ else if (lpc_did_hi_byte == 0x4d)
return PCH_JSP;
else
return PCH_UNKNOWN_SERIES;