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authorMeera Ravindranath <meera.ravindranath@intel.com>2020-04-27 22:40:03 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 06:17:21 +0000
commit798fd4b69fb8102d66ac58b6f6bec7f8cd5ea9de (patch)
tree7a9c9a3c9728a7dae71bb46d0a7c74b2bdd5dc45 /src/soc/intel
parentb8a0cd11c6cc509c122b09bafd911ce9c169d9c8 (diff)
downloadcoreboot-798fd4b69fb8102d66ac58b6f6bec7f8cd5ea9de.tar.xz
soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree. Filling this UPD will allow FSP to enable proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot jslrvp with NVMe Change-Id: Iad0b394fea019223a5b98fff0cb4a2bd1d2a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/jasperlake/chip.h3
-rw-r--r--src/soc/intel/jasperlake/fsp_params.c4
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 3983d03b84..a6932bc52c 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -110,6 +110,9 @@ struct soc_intel_jasperlake_config {
* clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
+ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
+ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
+
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 19b9300713..f525fd8af1 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -104,6 +104,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* disable Legacy PME */
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+ /* Enable ClkReqDetect for enabled port */
+ memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
+ sizeof(config->PcieRpClkReqDetect));
+
/* USB configuration */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {