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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-16 10:37:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-28 22:48:00 +0000
commit81100bf7ff62c4ee53214afb82f2fa9112d109b6 (patch)
tree8fdb92df42e60e200095aac64eb6b9781c54594f /src/soc/intel
parent4007d7f8c73d2872c6fe74f2b58a673161d6c947 (diff)
downloadcoreboot-81100bf7ff62c4ee53214afb82f2fa9112d109b6.tar.xz
soc/intel: Move fill_postcar_frame to memmap.c
Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/memmap.c30
-rw-r--r--src/soc/intel/apollolake/romstage.c29
-rw-r--r--src/soc/intel/baytrail/memmap.c15
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c13
-rw-r--r--src/soc/intel/cannonlake/memmap.c17
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c16
-rw-r--r--src/soc/intel/denverton_ns/memmap.c28
-rw-r--r--src/soc/intel/denverton_ns/romstage.c26
-rw-r--r--src/soc/intel/icelake/memmap.c17
-rw-r--r--src/soc/intel/icelake/romstage/romstage.c16
-rw-r--r--src/soc/intel/quark/memmap.c27
-rw-r--r--src/soc/intel/quark/romstage/fsp2_0.c25
-rw-r--r--src/soc/intel/skylake/memmap.c32
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c29
14 files changed, 166 insertions, 154 deletions
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index 8b51a85b76..bda43bbdbf 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -15,9 +15,11 @@
* GNU General Public License for more details.
*/
+#include <arch/romstage.h>
#include <assert.h>
#include <cbmem.h>
#include <console/console.h>
+#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/pci.h>
#include <soc/systemagent.h>
@@ -47,3 +49,31 @@ void smm_region(uintptr_t *start, size_t *size)
*start = sa_get_tseg_base();
*size = sa_get_tseg_size();
}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ uintptr_t smm_base;
+ size_t smm_size;
+
+ /*
+ * We need to make sure ramstage will be run cached. At this point exact
+ * location of ramstage in cbmem is not known. Instruct postcar to cache
+ * 16 megs under cbmem top which is a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t) cbmem_top();
+ /* cbmem_top() needs to be at least 16 MiB aligned */
+ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
+ postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB,
+ MTRR_TYPE_WRBACK);
+
+ /*
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
+ */
+ smm_region(&smm_base, &smm_size);
+ postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+}
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 7e369f46c8..29498656dc 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -24,7 +24,6 @@
#include <cbmem.h>
#include <cf9_reset.h>
#include <console/console.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/x86/pae.h>
#include <delay.h>
#include <cpu/x86/smm.h>
@@ -221,34 +220,6 @@ void mainboard_romstage_entry(void)
mainboard_save_dimm_info();
}
-void fill_postcar_frame(struct postcar_frame *pcf)
-{
- uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
-
- /*
- * We need to make sure ramstage will be run cached. At this point exact
- * location of ramstage in cbmem is not known. Instruct postcar to cache
- * 16 megs under cbmem top which is a safe bet to cover ramstage.
- */
- top_of_ram = (uintptr_t) cbmem_top();
- /* cbmem_top() needs to be at least 16 MiB aligned */
- assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
- postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB,
- MTRR_TYPE_WRBACK);
-
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
-}
-
static void fill_console_params(FSPM_UPD *mupd)
{
if (CONFIG(CONSOLE_SERIAL)) {
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c
index 015f13c503..d9f6160dfc 100644
--- a/src/soc/intel/baytrail/memmap.c
+++ b/src/soc/intel/baytrail/memmap.c
@@ -13,7 +13,9 @@
* GNU General Public License for more details.
*/
+#include <arch/romstage.h>
#include <cbmem.h>
+#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <soc/iosf.h>
@@ -37,3 +39,16 @@ void smm_region(uintptr_t *start, size_t *size)
*start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20;
*size = smm_region_size();
}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+
+ /* Cache at least 8 MiB below the top of ram, and at most 8 MiB
+ * above top of the ram. This satisfies MTRR alignment requirement
+ * with different TSEG size configurations.
+ */
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
+ MTRR_TYPE_WRBACK);
+}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 2b92c32f3a..80915fdca0 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -240,16 +240,3 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
{
romstage_main(base_timestamp);
}
-
-void fill_postcar_frame(struct postcar_frame *pcf)
-{
- uintptr_t top_of_ram;
-
- /* Cache at least 8 MiB below the top of ram, and at most 8 MiB
- * above top of the ram. This satisfies MTRR alignment requirement
- * with different TSEG size configurations.
- */
- top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
- postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
- MTRR_TYPE_WRBACK);
-}
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 276b9a356d..f0c21d96a5 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -14,9 +14,11 @@
* GNU General Public License for more details.
*/
+#include <arch/romstage.h>
#include <arch/ebda.h>
#include <cbmem.h>
#include <console/console.h>
+#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci.h>
@@ -264,3 +266,18 @@ void *cbmem_top(void)
return (void *)(uintptr_t)ebda_cfg.tolum_base;
}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ /*
+ * We need to make sure ramstage will be run cached. At this
+ * point exact location of ramstage in cbmem is not known.
+ * Instruct postcar to cache 16 megs under cbmem top which is
+ * a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t) cbmem_top();
+ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+ top_of_ram -= 16*MiB;
+ postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+}
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index fb5e42b200..ba583b9a6e 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -14,7 +14,6 @@
*/
#include <arch/romstage.h>
-#include <cpu/x86/mtrr.h>
#include <cbmem.h>
#include <console/console.h>
#include <fsp/util.h>
@@ -142,18 +141,3 @@ void mainboard_romstage_entry(void)
if (!s3wake)
save_dimm_info();
}
-
-void fill_postcar_frame(struct postcar_frame *pcf)
-{
- uintptr_t top_of_ram;
- /*
- * We need to make sure ramstage will be run cached. At this
- * point exact location of ramstage in cbmem is not known.
- * Instruct postcar to cache 16 megs under cbmem top which is
- * a safe bet to cover ramstage.
- */
- top_of_ram = (uintptr_t) cbmem_top();
- printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
- top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
-}
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index 0cca4b90d4..f7b2e07157 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -14,8 +14,10 @@
* GNU General Public License for more details.
*/
+#include <arch/romstage.h>
#include <cbmem.h>
#include <assert.h>
+#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci_def.h>
@@ -75,3 +77,29 @@ void smm_region(uintptr_t *start, size_t *size)
*start = smm_region_start();
*size = smm_region_size();
}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ uintptr_t smm_base;
+ size_t smm_size;
+
+ /*
+ * We need to make sure ramstage will be run cached. At this point exact
+ * location of ramstage in cbmem is not known. Instruct postcar to cache
+ * 16 megs under cbmem top which is a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t)cbmem_top();
+ postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
+ MTRR_TYPE_WRBACK);
+
+ /*
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
+ */
+ smm_region(&smm_base, &smm_size);
+ postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+}
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index cbd451ae0d..cb6ba11386 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -151,32 +151,6 @@ void mainboard_romstage_entry(void)
#endif
}
-void fill_postcar_frame(struct postcar_frame *pcf)
-{
- uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
-
- /*
- * We need to make sure ramstage will be run cached. At this point exact
- * location of ramstage in cbmem is not known. Instruct postcar to cache
- * 16 megs under cbmem top which is a safe bet to cover ramstage.
- */
- top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
- MTRR_TYPE_WRBACK);
-
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
-}
-
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
{
FSPM_UPD *mupd = container_of(m_cfg, FSPM_UPD, FspmConfig);
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 0d41f25280..71368c645a 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -13,9 +13,11 @@
* GNU General Public License for more details.
*/
+#include <arch/romstage.h>
#include <arch/ebda.h>
#include <cbmem.h>
#include <console/console.h>
+#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci.h>
@@ -262,3 +264,18 @@ void *cbmem_top(void)
return (void *)(uintptr_t)ebda_cfg.tolum_base;
}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ /*
+ * We need to make sure ramstage will be run cached. At this
+ * point exact location of ramstage in cbmem is not known.
+ * Instruct postcar to cache 16 megs under cbmem top which is
+ * a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t) cbmem_top();
+ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+ top_of_ram -= 16*MiB;
+ postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+}
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index a96f057d58..3d21a45e33 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -14,7 +14,6 @@
*/
#include <arch/romstage.h>
-#include <cpu/x86/mtrr.h>
#include <cbmem.h>
#include <console/console.h>
#include <fsp/util.h>
@@ -126,18 +125,3 @@ void mainboard_romstage_entry(void)
if (!s3wake)
save_dimm_info();
}
-
-void fill_postcar_frame(struct postcar_frame *pcf)
-{
- uintptr_t top_of_ram;
- /*
- * We need to make sure ramstage will be run cached. At this
- * point exact location of ramstage in cbmem is not known.
- * Instruct postcar to cache 16 megs under cbmem top which is
- * a safe bet to cover ramstage.
- */
- top_of_ram = (uintptr_t) cbmem_top();
- printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
- top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
-}
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
index d67856cc74..b8b85063a8 100644
--- a/src/soc/intel/quark/memmap.c
+++ b/src/soc/intel/quark/memmap.c
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
+#include <arch/romstage.h>
#include <cbmem.h>
#include <soc/reg_access.h>
@@ -32,3 +34,28 @@ void *cbmem_top(void)
/* Return the top of memory */
return (void *)top_of_memory;
}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ uintptr_t top_of_low_usable_memory;
+
+ /* Locate the top of RAM */
+ top_of_low_usable_memory = (uintptr_t) cbmem_top();
+ top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB);
+
+ /* Cache postcar and ramstage */
+ postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB,
+ MTRR_TYPE_WRBACK);
+
+ /* Cache RMU area */
+ postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory,
+ 0x10000, MTRR_TYPE_WRTHROUGH);
+
+ /* Cache ESRAM */
+ postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
+
+ pcf->skip_common_mtrr = 1;
+ /* Cache SPI flash - Write protect not supported */
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH);
+}
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index bd30271d77..57e35eeb3c 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -66,31 +66,6 @@ asmlinkage void car_stage_c_entry(void)
/* We do not return here. */
}
-void fill_postcar_frame(struct postcar_frame *pcf)
-{
- uintptr_t top_of_ram;
- uintptr_t top_of_low_usable_memory;
-
- /* Locate the top of RAM */
- top_of_low_usable_memory = (uintptr_t) cbmem_top();
- top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB);
-
- /* Cache postcar and ramstage */
- postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB,
- MTRR_TYPE_WRBACK);
-
- /* Cache RMU area */
- postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory,
- 0x10000, MTRR_TYPE_WRTHROUGH);
-
- /* Cache ESRAM */
- postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
-
- pcf->skip_common_mtrr = 1;
- /* Cache SPI flash - Write protect not supported */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH);
-}
-
static struct chipset_power_state power_state;
struct chipset_power_state *get_power_state(void)
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 9d3f377339..4c3c58a12d 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -14,10 +14,12 @@
* GNU General Public License for more details.
*/
+#include <arch/romstage.h>
#include <arch/ebda.h>
#include <device/mmio.h>
#include <cbmem.h>
#include <console/console.h>
+#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci.h>
@@ -289,3 +291,33 @@ void *cbmem_top(void)
return (void *)(uintptr_t)ebda_cfg.tolum_base;
}
+
+#if CONFIG(PLATFORM_USES_FSP2_0)
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ uintptr_t smm_base;
+ size_t smm_size;
+
+ /*
+ * We need to make sure ramstage will be run cached. At this
+ * point exact location of ramstage in cbmem is not known.
+ * Instruct postcar to cache 16 megs under cbmem top which is
+ * a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t) cbmem_top();
+ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+ top_of_ram -= 16*MiB;
+ postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+
+ /*
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
+ */
+ smm_region(&smm_base, &smm_size);
+ postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+}
+#endif
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 5388858449..ecd14289c2 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -16,7 +16,6 @@
#include <arch/romstage.h>
#include <arch/symbols.h>
#include <assert.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
@@ -154,34 +153,6 @@ void mainboard_romstage_entry(void)
save_dimm_info();
}
-void fill_postcar_frame(struct postcar_frame *pcf)
-{
- uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
-
- /*
- * We need to make sure ramstage will be run cached. At this
- * point exact location of ramstage in cbmem is not known.
- * Instruct postcar to cache 16 megs under cbmem top which is
- * a safe bet to cover ramstage.
- */
- top_of_ram = (uintptr_t) cbmem_top();
- printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
- top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
-
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
-}
-
static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
{
msr_t flex_ratio;