mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms

Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):

- mrc_cache_load_current: fetches the mrc_cache data and drops it into
  the given buffer.  This is useful for ARM platforms where the mmap
  operation is very expensive.

- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
  given buffer.  This is useful for platforms where the mmap operation
  is a no-op (like x86 platforms).  As the name mentions, we are not
  freeing the memory that we allocated with the mmap, so it is the
  caller's responsibility to do so.

Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot.  This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).

BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
     reboot from ec console.  Make sure memory training happens.
     reboot from ec console.  Make sure that we don't do training again.

Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 32 insertions, 25 deletions

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 54bdd2e24b..48ae9a726d 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -267,8 +267,6 @@ static void parse_devicetree_setting(FSPM_UPD *m_upd)
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
-	struct region_device rdev;
-
 	check_full_retrain(mupd);
 
 	fill_console_params(mupd);
@@ -310,11 +308,11 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	 * wrong/missing key renders DRAM contents useless.
 	 */
 
-	if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) {
-		/* Assume leaking is ok. */
-		assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
-		mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev);
-	}
+	mupd->FspmConfig.VariableNvsBufferPtr =
+		mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, version,
+					    NULL);
+
+	assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
 
 	fsp_version = version;
 
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 6ff6c03131..9a67c22e4b 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -122,8 +122,8 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 {
 	int ret;
 	mrc_wrapper_entry_t mrc_entry;
-	struct region_device rdev;
 	size_t i;
+	size_t mrc_size;
 
 	/* Fill in default entries. */
 	mp->version = MRC_PARAMS_VER;
@@ -135,11 +135,14 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 	if (!mp->io_hole_mb)
 		mp->io_hole_mb = 2048;
 
-	if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) {
-		mp->saved_data_size = region_device_sz(&rdev);
-		mp->saved_data = rdev_mmap_full(&rdev);
-		/* Assume boot device is memory mapped. */
-		assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
+	/* Assume boot device is memory mapped. */
+	assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
+
+	mp->saved_data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+						     0,
+						     &mrc_size);
+	if (mp->saved_data) {
+		mp->saved_data_size = mrc_size;
 	} else if (prev_sleep_state == ACPI_S3) {
 		/* If waking from S3 and no cache then. */
 		printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 4165c678d2..0580ca69b0 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -26,7 +26,7 @@
  */
 void raminit(struct pei_data *pei_data)
 {
-	struct region_device rdev;
+	size_t mrc_size;
 	struct memory_info *mem_info;
 	pei_wrapper_entry_t entry;
 	int ret;
@@ -39,19 +39,25 @@ void raminit(struct pei_data *pei_data)
 	    vboot_recovery_mode_enabled()) {
 		/* Recovery mode does not use MRC cache */
 		printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n");
-	} else if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) {
-		/* MRC cache found */
-		pei_data->saved_data_size = region_device_sz(&rdev);
-		pei_data->saved_data = rdev_mmap_full(&rdev);
+	} else {
 		/* Assume boot device is memory mapped. */
 		assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
-	} else if (pei_data->boot_mode == ACPI_S3) {
-		/* Waking from S3 and no cache. */
-		printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
-		post_code(POST_RESUME_FAILURE);
-		system_reset();
-	} else {
-		printk(BIOS_DEBUG, "No MRC cache found.\n");
+
+		pei_data->saved_data =
+			mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0,
+						    &mrc_size);
+		if (pei_data->saved_data) {
+			/* MRC cache found */
+			pei_data->saved_data_size = mrc_size;
+		} else if (pei_data->boot_mode == ACPI_S3) {
+			/* Waking from S3 and no cache. */
+			printk(BIOS_DEBUG,
+			       "No MRC cache found in S3 resume path.\n");
+			post_code(POST_RESUME_FAILURE);
+			system_reset();
+		} else {
+			printk(BIOS_DEBUG, "No MRC cache found.\n");
+		}
 	}
 
 	/*