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| author | Aaron Durbin <adurbin@chromium.org> | 2016-02-11 14:47:33 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-02-13 01:15:51 +0100 |
| commit | ada13ed4cbc519fde092dc54cda21e9d8ad94aa1 (patch) | |
| tree | 91af1273407accee77e0bf9469337461f8b2fdae /src/soc/intel | |
| parent | 65ac3d862f99c520b05da7c1ff66f4eaa336ad1d (diff) | |
| download | coreboot-ada13ed4cbc519fde092dc54cda21e9d8ad94aa1.tar.xz | |
soc/intel/apollolake: limit bootblock size to 32KiB
The CSE places the bootblock (IBBL in Intel parlance) below 4GiB
at top of the address space. However, it's size is limited to
32KiB. For now, just limit all of bootblock to 32KiB.
Change-Id: I8f84138fb81027eae1712b7af3943942c35cf0ea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13692
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index dcfbad65a8..bb0cc202da 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -75,4 +75,9 @@ config CONSOLE_UART_BASE_ADDRESS hex "MMIO base address for UART" default 0xde000000 +# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + endif |