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authorWonkyu Kim <wonkyu.kim@intel.com>2020-05-20 13:25:04 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:10:57 +0000
commitb4d7116a740b2847ef112cc1954462dac0b4cf85 (patch)
treefd3a6b827e1dad96e3dbb2f8ead747daef37e488 /src/soc/intel
parent165efa1b863ad8c35646beda6ddd76075c5674a2 (diff)
downloadcoreboot-b4d7116a740b2847ef112cc1954462dac0b4cf85.tar.xz
soc/intel/tigerlake: Delete unused configuration
Delete below configuration - Heci3Enabled: deprecated, see https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h#n442 - PchIshEnable: don't need as it's handled by devicetree dev on/off, see https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/romstage/fsp_params.c#n87 BUG:b:151166877 BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: If96cc7db7118dd6c2ac02aab3bb0c96763ffc722 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/tigerlake/chip.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 46c2d417a5..86e703b055 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -136,12 +136,6 @@ struct soc_intel_tigerlake_config {
/* SMBus */
uint8_t SmbusEnable;
- /* Integrated Sensor */
- uint8_t PchIshEnable;
-
- /* Heci related */
- uint8_t Heci3Enabled;
-
/* Gfx related */
uint8_t IgdDvmt50PreAlloc;
uint8_t InternalGfx;