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authorDuncan Laurie <dlaurie@chromium.org>2014-10-01 13:47:20 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-02 17:28:15 +0200
commitd9f95070650675599e0c1dee67f0b0074eced678 (patch)
tree611c5bf95691496a8556ff33d2923367e5b15079 /src/soc/intel
parent767d245ebf2d6d797bf759d23778553ed6f2a0b2 (diff)
downloadcoreboot-d9f95070650675599e0c1dee67f0b0074eced678.tar.xz
broadwell: Disable ADSP power gating feature by default
Disable ADSP D3 and SRAM power gating features by default, and make the devicetree.cb flags into enable flags instead of disable. BUG=chrome-os-partner:31588 BRANCH=samus,auron TEST=build and boot on samus Change-Id: Ibda298b995b07a2826a406e74e0d244b1fd97746 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b81ef37c036d61dc56e650796227dcc84a7ccc89 Original-Change-Id: Ib881290acc07819b55d776d4696bf0062df4d50e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220863 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9218 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/broadwell/adsp.c26
-rw-r--r--src/soc/intel/broadwell/chip.h5
2 files changed, 18 insertions, 13 deletions
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 9ecbe95b41..bf77763954 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -69,21 +69,25 @@ static void adsp_init(struct device *dev)
/* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0);
- if (config->adsp_d3_pg_disable) {
- if (pch_is_wpt()) {
- tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
- tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+ if (pch_is_wpt()) {
+ if (config->adsp_d3_pg_enable) {
+ tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
+ if (config->adsp_sram_pg_enable)
+ tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+ else
+ tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
} else {
- tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
- tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
}
} else {
- if (pch_is_wpt()) {
- tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
- tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
- } else {
+ if (config->adsp_d3_pg_enable) {
tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
- tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ if (config->adsp_sram_pg_enable)
+ tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ else
+ tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ } else {
+ tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
}
}
pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 005ab36551..703c865a8f 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -84,8 +84,9 @@ struct soc_intel_broadwell_config {
uint8_t sio_i2c0_voltage;
uint8_t sio_i2c1_voltage;
- /* Disable ADSP power gating in D3 */
- uint8_t adsp_d3_pg_disable;
+ /* Enable ADSP power gating features */
+ uint8_t adsp_d3_pg_enable;
+ uint8_t adsp_sram_pg_enable;
/*
* Clock Disable Map: