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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2014-04-09 12:45:57 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-10-28 18:08:43 +0100 |
| commit | dd20d5d36cc5350e834cad4052d9376bd29928a1 (patch) | |
| tree | d6871f2f20e9d0a4c91105649e85a42111de6d77 /src/soc/intel | |
| parent | b9590799b3aad8ef788f2c9afd7f6c2311ab169b (diff) | |
| download | coreboot-dd20d5d36cc5350e834cad4052d9376bd29928a1.tar.xz | |
baytrail: Remove unused devicetree fields
We're no longer configuring hotplug + backlight settings from
devicetree, so remove these entries + fields.
BUG=chrome-os-partner:27304
TEST=Compile only.
BRANCH=rambi+squawks
Change-Id: I7e27fbc070a9ea774e7dcbe551d61b1b1682a47f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193831
(cherry picked from commit 4ab13fd3aa2634673bb099bdfd714a21adc3caa0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7218
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/baytrail/chip.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 256ed4f2fa..0860a9666a 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -72,30 +72,19 @@ struct soc_intel_baytrail_config { /* Allow PCIe devices to wake system from suspend. */ int pcie_wake_enable; - /* - * Digital Port Hotplug Enable: - * 0x04 = Enabled, 2ms short pulse - * 0x05 = Enabled, 4.5ms short pulse - * 0x06 = Enabled, 6ms short pulse - * 0x07 = Enabled, 100ms short pulse - */ - int gpu_pipea_hotplug; int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ uint16_t gpu_pipea_power_on_delay; uint16_t gpu_pipea_light_on_delay; uint16_t gpu_pipea_power_off_delay; uint16_t gpu_pipea_light_off_delay; uint16_t gpu_pipea_power_cycle_delay; - uint32_t gpu_pipea_backlight_pwm; - int gpu_pipeb_hotplug; int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ uint16_t gpu_pipeb_power_on_delay; uint16_t gpu_pipeb_light_on_delay; uint16_t gpu_pipeb_power_off_delay; uint16_t gpu_pipeb_light_off_delay; uint16_t gpu_pipeb_power_cycle_delay; - uint32_t gpu_pipeb_backlight_pwm; }; extern struct chip_operations soc_intel_baytrail_ops; |