summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-11-27 11:20:57 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-11-02 06:17:41 +0000
commitfe9d2119a6181c0d04457effe8146933750927ef (patch)
treebef153fbf1da745b71049b4f7fc6f113ed1ab021 /src/soc/intel
parent087fe9fe2732db04ed62e9d49d5a84efe0656c8a (diff)
downloadcoreboot-fe9d2119a6181c0d04457effe8146933750927ef.tar.xz
soc/intel/fsp-car: Use the coreboot defined stack
The stack needs to be in the coreboot defined region to not collide with other symbols. Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index e77b841612..04dc5331e1 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -71,7 +71,7 @@ CAR_init_done:
jnz .halt_forever
/* Setup bootblock stack */
- mov %edx, %esp
+ movl $_ecar_stack, %esp
/*
* temp_memory_start/end reside in the .bss section, which gets cleared
* below. Save the FSP return value to the stack before writing those