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| author | Subrata Banik <subrata.banik@intel.com> | 2019-07-12 18:11:29 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-07-14 02:21:39 +0000 |
| commit | 270bb0a4c475057414b80c113648892aede570d0 (patch) | |
| tree | b33020312adba060b74710894793f4956ef7747e /src/soc/intel | |
| parent | 67d2a522148ea537cf87aeb0b369e143b11bb8c5 (diff) | |
| download | coreboot-270bb0a4c475057414b80c113648892aede570d0.tar.xz | |
soc/intel/icelake: Make use of PCH_DEVFN_HDA macro
Change-Id: I3be530072a6981760e9fe31e43741b4b480d045e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/icelake/romstage/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 420c427e7a..4801bd9ff9 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -38,7 +38,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SkipMbpHob = 1; /* If Audio Codec is enabled, enable FSP UPD */ - dev = pcidev_on_root(0x1f, 3); + dev = pcidev_path_on_root(PCH_DEVFN_HDA); if (!dev) m_cfg->PchHdaEnable = 0; else |