src/soc: Get rid of whitespace before tab

Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

17 files changed, 57 insertions, 57 deletions

diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/apollolake/exit_car_fsp.S
index 92289a0145..fbf2d31dc3 100644
--- a/src/soc/intel/apollolake/exit_car_fsp.S
+++ b/src/soc/intel/apollolake/exit_car_fsp.S
@@ -28,11 +28,11 @@
  * caching settings are based on an 8MiB Flash Size given as a
  * parameter to TempRamInit.
  *
- * 	TempRamExit MTRR Settings:
- * 	0x00000000  - 0x0009FFFF           | Write Back
- * 	0x000C0000  - Top of Low Memory    | Write Back
- * 	0xFF800000  - 0xFFFFFFFF Flash Reg | Write Protect
- * 	0x100000000 - Top of High Memory   | Write Back
+ *	TempRamExit MTRR Settings:
+ *	0x00000000  - 0x0009FFFF           | Write Back
+ *	0x000C0000  - Top of Low Memory    | Write Back
+ *	0xFF800000  - 0xFFFFFFFF Flash Reg | Write Protect
+ *	0x100000000 - Top of High Memory   | Write Back
  */
 
 .text
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h
index 580c4eb80b..93e80cbab2 100644
--- a/src/soc/intel/baytrail/include/soc/gpio.h
+++ b/src/soc/intel/baytrail/include/soc/gpio.h
@@ -58,8 +58,8 @@
 #define GPSSUS_COUNT		44
 
 /* GPIO legacy IO register settings */
-#define GPIO_USE_MMIO 		0
-#define GPIO_USE_LEGACY 	1
+#define GPIO_USE_MMIO		0
+#define GPIO_USE_LEGACY		1
 
 #define GPIO_DIR_OUTPUT		0
 #define GPIO_DIR_INPUT		1
@@ -317,12 +317,12 @@
 	{  .pad_conf0 = GPIO_LIST_END }
 
 /* Common default GPIO settings */
-#define GPIO_INPUT 		GPIO_INPUT_NOPU
+#define GPIO_INPUT		GPIO_INPUT_NOPU
 #define GPIO_INPUT_LEGACY	GPIO_INPUT_LEGACY_NOPU
 #define GPIO_INPUT_PU		GPIO_INPUT_PU_20K
-#define GPIO_INPUT_PD 		GPIO_INPUT_PD_20K
+#define GPIO_INPUT_PD		GPIO_INPUT_PD_20K
 #define GPIO_NC			GPIO_OUT_HIGH
-#define GPIO_DEFAULT 		GPIO_FUNC0
+#define GPIO_DEFAULT		GPIO_FUNC0
 
 /* 16 DirectIRQs per supported bank */
 #define GPIO_MAX_DIRQS	16
diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h
index e735f0116c..689d4d55cc 100644
--- a/src/soc/intel/baytrail/include/soc/msr.h
+++ b/src/soc/intel/baytrail/include/soc/msr.h
@@ -20,10 +20,10 @@
 #define MSR_BSEL_CR_OVERCLOCK_CONTROL	0xcd
 #define MSR_PLATFORM_INFO		0xce
 #define MSR_PMG_CST_CONFIG_CONTROL	0xe2
-#define 	SINGLE_PCTL			(1 << 11)
+#define	SINGLE_PCTL			(1 << 11)
 #define MSR_POWER_MISC			0x120
-#define 	ENABLE_ULFM_AUTOCM_MASK		(1 << 2)
-#define 	ENABLE_INDP_AUTOCM_MASK		(1 << 3)
+#define	ENABLE_ULFM_AUTOCM_MASK		(1 << 2)
+#define	ENABLE_INDP_AUTOCM_MASK		(1 << 3)
 #define MSR_IA32_PERF_CTL		0x199
 #define MSR_IA32_MISC_ENABLES		0x1a0
 #define MSR_POWER_CTL			0x1fc
diff --git a/src/soc/intel/baytrail/include/soc/xhci.h b/src/soc/intel/baytrail/include/soc/xhci.h
index ec643c1725..d509b51a6a 100644
--- a/src/soc/intel/baytrail/include/soc/xhci.h
+++ b/src/soc/intel/baytrail/include/soc/xhci.h
@@ -33,7 +33,7 @@
 # define  XHCI_USB3_PORTSC_WOE	  (1 << 27)  /* Wake on Overcurrent */
 # define  XHCI_USB3_PORTSC_WRC	  (1 << 19)  /* Warm Reset Complete */
 # define  XHCI_USB3_PORTSC_LWS	  (1 << 16)  /* Link Write Strobe */
-# define  XHCI_USB3_PORTSC_PED 	  (1 << 1)   /* Port Enabled/Disabled */
+# define  XHCI_USB3_PORTSC_PED	  (1 << 1)   /* Port Enabled/Disabled */
 # define  XHCI_USB3_PORTSC_WPR	  (1 << 31)  /* Warm Port Reset */
 # define  XHCI_USB3_PORTSC_PLS	  (0xf << 5) /* Port Link State */
 # define   XHCI_PLSR_DISABLED	  (4 << 5)   /* Port is disabled */
diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c
index 61e95fabc9..e1e7542ed8 100644
--- a/src/soc/intel/baytrail/romstage/early_spi.c
+++ b/src/soc/intel/baytrail/romstage/early_spi.c
@@ -22,7 +22,7 @@
 #include <soc/romstage.h>
 #include <soc/spi.h>
 
-#define SPI_CYCLE_DELAY 10 				/* 10us */
+#define SPI_CYCLE_DELAY 10				/* 10us */
 #define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY	/* 400ms */
 
 #define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x))
diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl
index 76804f8b8a..ef0eaba476 100644
--- a/src/soc/intel/broadwell/acpi/pch.asl
+++ b/src/soc/intel/broadwell/acpi/pch.asl
@@ -31,7 +31,7 @@ Scope (\)
 	Field (RCRB, DWordAcc, Lock, Preserve)
 	{
 		Offset (0x3404), // High Performance Timer Configuration
-		HPAS, 2, 	// Address Select
+		HPAS, 2,	// Address Select
 		, 5,
 		HPTE, 1,	// Address Enable
 	}
diff --git a/src/soc/intel/broadwell/acpi/pci_irqs.asl b/src/soc/intel/broadwell/acpi/pci_irqs.asl
index 6565334fdf..44263ea6ab 100644
--- a/src/soc/intel/broadwell/acpi/pci_irqs.asl
+++ b/src/soc/intel/broadwell/acpi/pci_irqs.asl
@@ -29,11 +29,11 @@ Method(_PRT)
 			Package() { 0x001cffff, 1, 0, 17 },
 			Package() { 0x001cffff, 2, 0, 18 },
 			Package() { 0x001cffff, 3, 0, 19 },
-			// EHCI	  			0:1d.0
+			// EHCI				0:1d.0
 			Package() { 0x001dffff, 0, 0, 19 },
 			// Audio DSP (Smart Sound)	0:13.0
 			Package() { 0x0013ffff, 0, 0, 23 },
-			// XHCI	  			0:14.0
+			// XHCI				0:14.0
 			Package() { 0x0014ffff, 0, 0, 18 },
 			// LPC devices			0:1f.0
 			Package() { 0x001fffff, 0, 0, 22 },
@@ -61,11 +61,11 @@ Method(_PRT)
 			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
 			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
 			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	  			0:1d.0
+			// EHCI				0:1d.0
 			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
 			// Audio DSP (Smart Sound)	0:13.0
 			Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
-			// XHCI	  			0:14.0
+			// XHCI				0:14.0
 			Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
 			// LPC device			0:1f.0
 			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index b794ede967..90cd3701b5 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -39,7 +39,7 @@
 #define   SUS_PWR_FLR			(1 << 16)
 #define   PME_B0_S5_DIS			(1 << 15)
 #define   PWR_FLR			(1 << 14)
-#define   ALLOW_L1LOW_BCLKREQ_ON 	(1 << 13)
+#define   ALLOW_L1LOW_BCLKREQ_ON	(1 << 13)
 #define   DIS_SLP_X_STRCH_SUS_UP	(1 << 12)
 #define   SLP_S3_MIN_ASST_WDTH_MASK	(3 << 10)
 #define     SLP_S3_MIN_ASST_WDTH_60USEC	(0 << 10)
diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c
index 512fbbe0f3..26f0a632a0 100644
--- a/src/soc/intel/cannonlake/reset.c
+++ b/src/soc/intel/cannonlake/reset.c
@@ -69,7 +69,7 @@ static int send_heci_reset_message(void)
 	reply_size = sizeof(reply);
 	memset(&reply, 0, reply_size);
 	if (!heci_receive(&reply, &reply_size))
-        	return -1;
+		return -1;
 	if (reply.result != MKHI_STATUS_SUCCESS) {
 		printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n");
 		return -1;
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 02aeefe9ab..684f82786a 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -94,7 +94,7 @@ clear_var_mtrr:
 	 *  MTRR_PHYS_MASK_HIGH = 0000000FFh  For 40 bit addressing
 	 */
 
-	movl	$0x80000008, %eax 	/* Address sizes leaf */
+	movl	$0x80000008, %eax	/* Address sizes leaf */
 	cpuid
 	sub	$32, %al
 	movzx	%al, %eax
@@ -193,7 +193,7 @@ car_init_done:
 	movd	%mm2, %eax
 	pushl	%eax	/* tsc[63:32] */
 	movd	%mm1, %eax
-	pushl	%eax 	/* tsc[31:0] */
+	pushl	%eax	/* tsc[31:0] */
 
 before_carstage:
 	post_code(0x2A)
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
index a389e34154..2ae56dfa7b 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
@@ -22,7 +22,7 @@
 #define SPIBAR_BIOS_CONTROL		0xdc
 
 /* Bit definitions for BIOS_CONTROL */
-#define SPIBAR_BIOS_CONTROL_WPD 	(1 << 0)
+#define SPIBAR_BIOS_CONTROL_WPD		(1 << 0)
 #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE	(1 << 1)
 #define SPIBAR_BIOS_CONTROL_CACHE_DISABLE	(1 << 2)
 #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE	(1 << 3)
@@ -113,21 +113,21 @@
 #define SPIBAR_FPR_MAX			5
 
 /* Programmable values for OPMENU_LOWER(0xA8) & OPMENU_UPPER(0xAC) register */
-#define SPI_OPMENU_0 			0x01 /* WRSR: Write Status Register */
-#define SPI_OPTYPE_0 			0x01 /* Write, no address */
-#define SPI_OPMENU_1 			0x02 /* BYPR: Byte Program */
-#define SPI_OPTYPE_1 			0x03 /* Write, address required */
-#define SPI_OPMENU_2 			0x03 /* READ: Read Data */
-#define SPI_OPTYPE_2 			0x02 /* Read, address required */
-#define SPI_OPMENU_3 			0x05 /* RDSR: Read Status Register */
-#define SPI_OPTYPE_3 			0x00 /* Read, no address */
-#define SPI_OPMENU_4 			0x20 /* SE20: Sector Erase 0x20 */
-#define SPI_OPTYPE_4 			0x03 /* Write, address required */
-#define SPI_OPMENU_5 			0x9f /* RDID: Read ID */
-#define SPI_OPTYPE_5 			0x00 /* Read, no address */
-#define SPI_OPMENU_6 			0xd8 /* BED8: Block Erase 0xd8 */
-#define SPI_OPTYPE_6 			0x03 /* Write, address required */
-#define SPI_OPMENU_7 			0x0b /* FAST: Fast Read */
+#define SPI_OPMENU_0			0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0			0x01 /* Write, no address */
+#define SPI_OPMENU_1			0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1			0x03 /* Write, address required */
+#define SPI_OPMENU_2			0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2			0x02 /* Read, address required */
+#define SPI_OPMENU_3			0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3			0x00 /* Read, no address */
+#define SPI_OPMENU_4			0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4			0x03 /* Write, address required */
+#define SPI_OPMENU_5			0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5			0x00 /* Read, no address */
+#define SPI_OPMENU_6			0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6			0x03 /* Write, address required */
+#define SPI_OPMENU_7			0x0b /* FAST: Fast Read */
 #define SPI_OPTYPE_7			0x02 /* Read, address required */
 #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
 			  (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c
index 66eaddf5eb..811d27354e 100644
--- a/src/soc/intel/common/block/scs/sd.c
+++ b/src/soc/intel/common/block/scs/sd.c
@@ -57,7 +57,7 @@ static void sd_fill_ssdt(struct device *dev)
 static struct device_operations dev_ops = {
 	.read_resources			= &pci_dev_read_resources,
 	.set_resources			= &pci_dev_set_resources,
-	.enable_resources	 	= &pci_dev_enable_resources,
+	.enable_resources		= &pci_dev_enable_resources,
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 	.acpi_fill_ssdt_generator	= &sd_fill_ssdt,
 #endif
diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl
index 262ac55cba..3167c183d8 100644
--- a/src/soc/intel/denverton_ns/acpi/lpc.asl
+++ b/src/soc/intel/denverton_ns/acpi/lpc.asl
@@ -177,7 +177,7 @@ Device (LPCB)
 		Name(BUF0,ResourceTemplate()
 		{
 		  IO(Decode16,0x02F8,0x02F8,0x01,0x08)
- 		  Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {17}
+		  Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {17}
 		})
 		Return(BUF0)
 	  }
diff --git a/src/soc/intel/denverton_ns/exit_car_fsp.S b/src/soc/intel/denverton_ns/exit_car_fsp.S
index 2ec625b4d2..83d5a330e7 100644
--- a/src/soc/intel/denverton_ns/exit_car_fsp.S
+++ b/src/soc/intel/denverton_ns/exit_car_fsp.S
@@ -29,11 +29,11 @@
  * caching settings are based on an 8MiB Flash Size given as a
  * parameter to TempRamInit.
  *
- * 	TempRamExit MTRR Settings:
- * 	0x00000000  - 0x0009FFFF           | Write Back
- * 	0x000C0000  - Top of Low Memory    | Write Back
- * 	0xFF800000  - 0xFFFFFFFF Flash Reg | Write Protect
- * 	0x100000000 - Top of High Memory   | Write Back
+ *	TempRamExit MTRR Settings:
+ *	0x00000000  - 0x0009FFFF           | Write Back
+ *	0x000C0000  - Top of Low Memory    | Write Back
+ *	0xFF800000  - 0xFFFFFFFF Flash Reg | Write Protect
+ *	0x100000000 - Top of High Memory   | Write Back
  */
 
 .text
diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
index 7c81151b51..767755454b 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
@@ -56,8 +56,8 @@
 #define GPSSUS_COUNT		44
 
 /* GPIO legacy IO register settings */
-#define GPIO_USE_MMIO 		0
-#define GPIO_USE_LEGACY 	1
+#define GPIO_USE_MMIO		0
+#define GPIO_USE_LEGACY		1
 
 #define GPIO_DIR_OUTPUT		0
 #define GPIO_DIR_INPUT		1
@@ -291,12 +291,12 @@
 	{  .pad_conf0 = GPIO_LIST_END }
 
 /* Common default GPIO settings */
-#define GPIO_INPUT 	GPIO_INPUT_NOPU
+#define GPIO_INPUT	GPIO_INPUT_NOPU
 #define GPIO_INPUT_LEGACY	GPIO_INPUT_LEGACY_NOPU
 #define GPIO_INPUT_PU	GPIO_INPUT_PU_20K
-#define GPIO_INPUT_PD 	GPIO_INPUT_PD_20K
+#define GPIO_INPUT_PD	GPIO_INPUT_PD_20K
 #define GPIO_NC			GPIO_INPUT_PU_20K
-#define GPIO_DEFAULT 	GPIO_FUNC0
+#define GPIO_DEFAULT	GPIO_FUNC0
 
 /* 16 DirectIRQs per supported bank */
 #define GPIO_MAX_DIRQS	16
diff --git a/src/soc/intel/fsp_baytrail/include/soc/xhci.h b/src/soc/intel/fsp_baytrail/include/soc/xhci.h
index ec643c1725..d509b51a6a 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/xhci.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/xhci.h
@@ -33,7 +33,7 @@
 # define  XHCI_USB3_PORTSC_WOE	  (1 << 27)  /* Wake on Overcurrent */
 # define  XHCI_USB3_PORTSC_WRC	  (1 << 19)  /* Warm Reset Complete */
 # define  XHCI_USB3_PORTSC_LWS	  (1 << 16)  /* Link Write Strobe */
-# define  XHCI_USB3_PORTSC_PED 	  (1 << 1)   /* Port Enabled/Disabled */
+# define  XHCI_USB3_PORTSC_PED	  (1 << 1)   /* Port Enabled/Disabled */
 # define  XHCI_USB3_PORTSC_WPR	  (1 << 31)  /* Warm Port Reset */
 # define  XHCI_USB3_PORTSC_PLS	  (0xf << 5) /* Port Link State */
 # define   XHCI_PLSR_DISABLED	  (4 << 5)   /* Port is disabled */
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index 1abe9cb884..600be27957 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -25,7 +25,7 @@
 #include <string.h>
 
 #define PCR_DMI_GCS		0x274C
-#define PCR_DMI_GCS_BILD  	(1 << 0)
+#define PCR_DMI_GCS_BILD	(1 << 0)
 
 static void lpc_lockdown_config(const struct soc_intel_skylake_config *config)
 {
@@ -56,9 +56,9 @@ static void dmi_lockdown_config(void)
 	 * When set, prevents GCS.BBS from being changed
 	 * GCS.BBS: (Boot BIOS Strap) This field determines the destination
 	 * of accesses to the BIOS memory range.
-	 * 	Bits Description
-	 * 	"0b": SPI
-	 * 	"1b": LPC/eSPI
+	 *	Bits Description
+	 *	"0b": SPI
+	 *	"1b": LPC/eSPI
 	 */
 	pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
 }