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| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-04-01 15:56:11 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-11 20:28:26 +0000 |
| commit | 083379d0f8a8524c4ffc708350c3e2c9fae683af (patch) | |
| tree | c044cd2af2d06918a8c59b93db50bac2ef434127 /src/soc/intel | |
| parent | 32107dffb7013095f45f363fddcf8a3215790199 (diff) | |
| download | coreboot-083379d0f8a8524c4ffc708350c3e2c9fae683af.tar.xz | |
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527
Update FSP headers for Tiger Lake platform generated based FSP
version 2527. Which includes below additional UPDs:
FSPM:
- PchTraceHubMode
- CpuTraceHubMode
- CpuPcieRpEnableMask
FSPS:
- D3HotEnable
- D3ColdEnable
- RtcMemoryLock
- PchLockDownGlobalSmi
- PchLockDownBiosInterface
- PchUnlockGpioPads
- CpuMpPpi
- ThcPort0Assignment
- ThcPort1Assignment
BUG=b:150357377
BRANCH=none
TEST=build and boot ripto/volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40026
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions