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authorDivagar Mohandass <divagar.mohandass@intel.com>2016-02-08 16:09:21 +0530
committerMartin Roth <martinroth@google.com>2017-09-08 21:07:53 +0000
commit0c68530f15df0f027adb664cca0c3fcf0de2233a (patch)
tree30b5caa75a5c7ac594b0bcd0d2fe44efa6bac005 /src/soc/intel
parent77c01e1f2f16bc24a45e68b0c413e510dc19a756 (diff)
downloadcoreboot-0c68530f15df0f027adb664cca0c3fcf0de2233a.tar.xz
soc/intel/braswell: Add I2C clock config options
Cherry-pick from Chromium commit e3c1ec2. This change includes - FSP config parameters to configure I2C clock speed. - Options are 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz and default is 400Khz. Original-Change-Id: Iab2bf3997102908583078f5f1d185d6c66561390 Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ifae3ba4262cb3cc6416ce5054614ed7765e22c25 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/braswell/chip.c7
-rw-r--r--src/soc/intel/braswell/chip.h7
2 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 4d7b90688c..91cb3843bf 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -162,6 +162,13 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->ISPEnable = config->ISPEnable;
params->ISPPciDevConfig = config->ISPPciDevConfig;
params->PcdSdDetectChk = config->PcdSdDetectChk;
+ params->I2C0Frequency = config->I2C0Frequency;
+ params->I2C1Frequency = config->I2C1Frequency;
+ params->I2C2Frequency = config->I2C2Frequency;
+ params->I2C3Frequency = config->I2C3Frequency;
+ params->I2C4Frequency = config->I2C4Frequency;
+ params->I2C5Frequency = config->I2C5Frequency;
+ params->I2C6Frequency = config->I2C6Frequency;
}
void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 8c3f143b46..c661bb402a 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -161,6 +161,13 @@ struct soc_intel_braswell_config {
UINT8 ISPEnable;
UINT8 ISPPciDevConfig;
UINT8 PcdSdDetectChk; /*Enable\Disable SD Card Detect Simulation*/
+ UINT8 I2C0Frequency; /* 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz */
+ UINT8 I2C1Frequency;
+ UINT8 I2C2Frequency;
+ UINT8 I2C3Frequency;
+ UINT8 I2C4Frequency;
+ UINT8 I2C5Frequency;
+ UINT8 I2C6Frequency;
};
extern struct chip_operations soc_intel_braswell_ops;