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authorElyes HAOUAS <ehaouas@noos.fr>2020-05-27 16:21:55 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-06-06 09:43:11 +0000
commit379aab47f9bf4a804de168b61d3b2a1f6f789a91 (patch)
tree4b2435a2a04d78cdc40b641efc19431d966c53c0 /src/soc/intel
parentcecc4a0d7a458b08808fbe818054408691896eea (diff)
downloadcoreboot-379aab47f9bf4a804de168b61d3b2a1f6f789a91.tar.xz
src: Remove unused 'include <cpu/x86/mtrr.h>'
Change-Id: I3f08b9cc34582165785063580b3356135030f63e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/broadwell/bootblock/cpu.c1
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S1
-rw-r--r--src/soc/intel/common/block/cpu/car/exit_car_fsp.S1
-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c1
-rw-r--r--src/soc/intel/denverton_ns/bootblock/bootblock.c1
-rw-r--r--src/soc/intel/denverton_ns/romstage.c1
-rw-r--r--src/soc/intel/quark/include/soc/reg_access.h1
-rw-r--r--src/soc/intel/xeon_sp/skx/romstage.c1
8 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c
index 79f859bec3..d6883c6436 100644
--- a/src/soc/intel/broadwell/bootblock/cpu.c
+++ b/src/soc/intel/broadwell/bootblock/cpu.c
@@ -4,7 +4,6 @@
#include <arch/bootblock.h>
#include <arch/io.h>
#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
#include <halt.h>
#include <soc/rcba.h>
#include <soc/msr.h>
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index 393d612d3c..b9daf08b2f 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <device/pci_def.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/x86/cr.h>
#include <cpu/x86/post_code.h>
diff --git a/src/soc/intel/common/block/cpu/car/exit_car_fsp.S b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S
index e5798fb6cc..fd79e8eb4e 100644
--- a/src/soc/intel/common/block/cpu/car/exit_car_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <cpu/x86/mtrr.h>
#include <cpu/x86/cr.h>
/*
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 7201432301..dac654fea6 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -4,7 +4,6 @@
#include <console/console.h>
#include <cpu/intel/turbo.h>
#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
#include <arch/cpu.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index cabcdedc93..76db62e3fd 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
-#include <cpu/x86/mtrr.h>
#include <device/pci.h>
#include <FsptUpd.h>
#include <intelblocks/fast_spi.h>
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index abfd3dee10..713fb1e3ac 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -5,7 +5,6 @@
#include <cbmem.h>
#include <cf9_reset.h>
#include <console/console.h>
-#include <cpu/x86/mtrr.h>
#include <device/pci_ops.h>
#include <soc/fiamux.h>
#include <device/mmio.h>
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h
index 9693b725fb..31df09d7c5 100644
--- a/src/soc/intel/quark/include/soc/reg_access.h
+++ b/src/soc/intel/quark/include/soc/reg_access.h
@@ -5,7 +5,6 @@
#include <cpu/x86/cr.h>
#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
#include <fsp/util.h>
#include <reg_script.h>
#include <soc/IntelQNCConfig.h>
diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c
index 18dc81438c..c4c473b4e6 100644
--- a/src/soc/intel/xeon_sp/skx/romstage.c
+++ b/src/soc/intel/xeon_sp/skx/romstage.c
@@ -3,7 +3,6 @@
#include <arch/romstage.h>
#include <cbmem.h>
#include <console/console.h>
-#include <cpu/x86/mtrr.h>
#include <intelblocks/rtc.h>
#include <soc/romstage.h>
#include <soc/soc_util.h>