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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-07-16 12:56:03 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-21 17:30:24 +0000 |
| commit | 498de91e459bc5122fb72d2a486e1d74d17eaac5 (patch) | |
| tree | 62ebd7be641a6efa1adf29dc47058107c6b9fd30 /src/soc/intel | |
| parent | 917cc5cf2529f1ce387354941fb0a664919e8a91 (diff) | |
| download | coreboot-498de91e459bc5122fb72d2a486e1d74d17eaac5.tar.xz | |
soc/amd/picasso: Enable stage cache only with ACPI resume
Make the option match the change in I7c3b3ec.
"stoneyridge/Kconfig: Enable stage cache based on HAVE_ACPI_RESUME"
Change-Id: I7fa13428ec0119b61f429116a52986067e833bdf
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions