diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-04-07 23:37:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-14 09:52:33 +0000 |
| commit | 53ac68e5518472612c1c4b5adf40d068fa3d7dda (patch) | |
| tree | 6bca911846f6837d8904c02536905e5d9d5fc726 /src/soc/intel | |
| parent | e3bf8ba2d812dd027afa8ee8ff368a5295ce1bda (diff) | |
| download | coreboot-53ac68e5518472612c1c4b5adf40d068fa3d7dda.tar.xz | |
mb/intel/tglrvp : Enable RP LTR
BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40269
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions