baytrail: romstage: Add function to check SW WP status for vboot

Implement vboot_get_sw_write_protect, which returns the FW SPI ROM SW WP
status.

BUG=chrome-os-partner:26777
TEST=Manual on Rambi with all patches in sequence:
`crossystem sw_wpsw_boot` prints 0
`flashrom --wp-enable` + reboot
`crossystem sw_wpsw_boot` prints 1
BRANCH=Rambi

Original-Change-Id: I5da35c1b2d25b8679bf0084af65d08de224387f8
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/190097
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5bba447654417c42952c49542ed047b4867d04d1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I739cbb8fca5f02462cf78c81f9b364aabfd3fe86
Reviewed-on: http://review.coreboot.org/7211
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

5 files changed, 83 insertions, 0 deletions

diff --git a/src/soc/intel/baytrail/baytrail/romstage.h b/src/soc/intel/baytrail/baytrail/romstage.h
index 43c60eccc7..9ea3564fa3 100644
--- a/src/soc/intel/baytrail/baytrail/romstage.h
+++ b/src/soc/intel/baytrail/baytrail/romstage.h
@@ -50,6 +50,7 @@ void gfx_init(void);
 void tco_disable(void);
 void punit_init(void);
 void set_max_freq(void);
+int early_spi_read_wpsr(u8 *sr);
 
 #if CONFIG_ENABLE_BUILTIN_COM1
 void byt_config_com1_and_enable(void);
diff --git a/src/soc/intel/baytrail/baytrail/spi.h b/src/soc/intel/baytrail/baytrail/spi.h
index 9c0c29d53b..ef71ad5a79 100644
--- a/src/soc/intel/baytrail/baytrail/spi.h
+++ b/src/soc/intel/baytrail/baytrail/spi.h
@@ -24,7 +24,14 @@
 
 /* These registers live behind SPI_BASE_ADDRESS. */
 #define HSFSTS				0x04
+#define FDATA0				0x10
 # define FLOCKDN			(0x1 << 15)
+#define SSFS				0x90
+# define CYCLE_DONE_STATUS		(0x1 << 2)
+# define FLASH_CYCLE_ERROR		(0x1 << 3)
+#define SSFC				0x91
+# define SPI_CYCLE_GO			(0x1 << 1)
+# define DATA_CYCLE			(0x1 << 14)
 #define PREOP				0x94
 #define OPTYPE				0x96
 #define OPMENU0				0x98
diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc
index b8eeb41a06..345037d51f 100644
--- a/src/soc/intel/baytrail/romstage/Makefile.inc
+++ b/src/soc/intel/baytrail/romstage/Makefile.inc
@@ -4,3 +4,4 @@ romstage-y += raminit.c
 romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
 romstage-y += gfx.c
 romstage-y += pmc.c
+romstage-y += early_spi.c
\ No newline at end of file
diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c
new file mode 100644
index 0000000000..6188f075fc
--- /dev/null
+++ b/src/soc/intel/baytrail/romstage/early_spi.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <delay.h>
+#include <console/console.h>
+
+#include <baytrail/iomap.h>
+#include <baytrail/romstage.h>
+#include <baytrail/spi.h>
+
+#define SPI_CYCLE_DELAY 10 				/* 10us */
+#define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY	/* 400ms */
+
+#define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x))
+#define SPI16(x) *((volatile u16 *)(SPI_BASE_ADDRESS + x))
+#define SPI32(x) *((volatile u32 *)(SPI_BASE_ADDRESS + x))
+
+/* Minimal set of commands to read wpsr from SPI. Don't use this code outside
+ * romstage -- it trashes the opmenu table.
+ * Returns 0 on success, < 0 on failure. */
+int early_spi_read_wpsr(u8 *sr)
+{
+	int timeout = SPI_CYCLE_TIMEOUT;
+
+	/* No address associated with rdsr */
+	SPI8(OPTYPE) = 0x0;
+	/* Setup opcode[0] = read wpsr */
+	SPI8(OPMENU0) = 0x5;
+
+	/* Start transaction */
+	SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO;
+
+	/* Wait for error / complete status */
+	while(timeout--) {
+		u16 status = SPI16(SSFS);
+		if (status & FLASH_CYCLE_ERROR) {
+			printk(BIOS_ERR, "SPI rdsr failed\n");
+			return -1;
+		} else if (status & CYCLE_DONE_STATUS)
+			break;
+
+		udelay(SPI_CYCLE_DELAY);
+	}
+
+	*sr = SPI32(FDATA0) & 0xff;
+	return 0;
+}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 1c08f339fd..b69b532e31 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -393,3 +393,12 @@ void ramstage_cache_invalid(struct ramstage_cache *cache)
 	cold_reset();
 #endif
 }
+
+#if CONFIG_CHROMEOS
+int vboot_get_sw_write_protect(void)
+{
+	u8 status;
+	/* Return unprotected status if status read fails. */
+	return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
+}
+#endif