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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-12-29 09:40:40 +0200 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2019-01-06 13:19:05 +0000 |
commit | 63649d24fd616dad397a4ae18f9aede43c6ce2dc (patch) | |
tree | df6c66c50a330d79d81c315f43547f0fdc45978e /src/soc/intel | |
parent | a144e4d6fa93b9ba129b3aa8991cc5fb2ec3c8a6 (diff) | |
download | coreboot-63649d24fd616dad397a4ae18f9aede43c6ce2dc.tar.xz |
usbdebug: Refactor init calls
Expose the function that can unconditionally re-initialise
EHCI debug host and gadget.
Given the missing header in soc/intel files that prevented
building with USBDEBUG_IN_ROMSTAGE=y, it is not actually
known if those SOCs work at all for usbdebug.
Change-Id: I8ae7e144a89a8f7e5f9d307ba4e73d4f96401a79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel')
-rw-r--r-- | src/soc/intel/fsp_baytrail/romstage/romstage.c | 6 | ||||
-rw-r--r-- | src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index bc49a418f4..15ab9ec949 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -20,6 +20,7 @@ #include <arch/cbfs.h> #include <arch/early_variables.h> #include <console/console.h> +#include <console/usb.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> @@ -225,10 +226,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); -#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* FSP reconfigures USB, so reinit it to have debug */ - usbdebug_init(); -#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */ + if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) + usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 801f9e0e5e..924aab2a25 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -21,6 +21,7 @@ #include <arch/cbfs.h> #include <cbmem.h> #include <console/console.h> +#include <console/usb.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <romstage_handoff.h> @@ -101,10 +102,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); -#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* FSP reconfigures USB, so reinit it to have debug */ - usbdebug_init(); -#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */ + if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) + usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); |