fsp1_1: provide binding to UEFI version

FSP has some unique attributes which makes integration
cumbersome:

1. FSP header files do not include the types they need. Like
   EDKII development it's expected types are provided by the
   build system. Therefore, one needs to include the proper
   files to avoid compilation issues.
2. An implementation of FSP for a chipset may use different
   versions of the UEFI PI spec implementation. EDKII is a
   proxy for all of UEFI specifications. In order to provide
   flexibility one needs to binding a set of types and
   structures from an UEFI PI implementation.
3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h
   file which defines it's own types. Commonality between
   FSP chipset implementations are only named typedef
   structs. The fields within are not consistent. And
   because of FSP's insistence on typedefs it makes it
   near impossible to forward declare structs.

The above 3 means one needs to include the correct UEFI
type bindings when working with FSP. The current
implementation had the SoC picking include paths in the
edk2 directory and using a bare <uefi_types.h> include.
Also, with the prior fsp_util.h implementation the SoC's
FSP FspUpdVpd.h header file was required since for providing
all the types at once (Generic FSP 1.1 and SoC types).

The binding has been changed in the following manner:
1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1
   selects. No other bindings are currently available,
   but this provides the policy.
2. Based on CONFIG_UEFI_2_4_BINDING the proper include
   paths are added to the CPPFLAGS_common.
3. SoC Makefile.inc does not bind UEFI types nor does
   it adjust CPPFLAGS_common in any way.
4. Provide a include/fsp directory under fsp1_1 and
   expose src/drivers/intel/fsp1_1/include in the
   include path. This split can allow a version 2,
   for example, FSP to provide its own include files.
   Yes, that means there needs to be consistency in
   APIs, however that's not this patch.
5. Provide a way for code to differentiate the FSP spec
   types (fsp/api.h) from the chipset FSP types
   (fsp/soc_binding.h). This allows for code re-use that
   doesn't need the chipset types to be defined such as
   the FSP relocation code.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted on glados.

Signed-off-by: Aaron Durbin <adubin@chromium.org>

Change-Id: I894165942cfe36936e186af5221efa810be8bb29
Reviewed-on: http://review.coreboot.org/11606
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)

18 files changed, 14 insertions, 114 deletions

diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 755c15a0cf..fae97b8219 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -51,19 +51,11 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += tsc_freq.c
 
-CPPFLAGS_common += -I$(src)/arch/x86/include/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index e1065e22d1..b8be3c6fec 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -35,7 +35,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <ec/google/chromeec/ec.h>
-#include <fsp_gop.h>
+#include <fsp/gop.h>
 #include <rules.h>
 #include <soc/acpi.h>
 #include <soc/gfx.h>
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index c986507968..6f227407de 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -22,7 +22,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 191fc01926..ff68014d9c 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -27,7 +27,7 @@
 #define _SOC_CHIP_H_
 
 #include <stdint.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 
 #define SVID_CONFIG1		1
diff --git a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h b/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
deleted file mode 100644
index c269a613aa..0000000000
--- a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef CHIPSET_FSP_UTIL_H
-#define CHIPSET_FSP_UTIL_H
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h>				/* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h>		/* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h>	/* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h>	/* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>	/* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>	/* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>	/* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h>		/* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h>	/* HOB routine declarations */
-#include <FspUpdVpd.h>		/* Vital/updatable product data definitions */
-
-#endif	/* CHIPSET_FSP_UTIL_H */
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 770a39d115..a735c04db5 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -23,7 +23,7 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>
 #include <soc/intel/common/romstage.h>
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 7821a2a1ca..390e050ab8 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -25,7 +25,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/memmap.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 3e1e02fb19..26c23bc486 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -29,7 +29,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <romstage_handoff.h>
 #include <soc/gpio.h>
 #include <soc/lpc.h>
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 1dbff5478e..2286cd48e7 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -40,7 +40,7 @@
 #include <timestamp.h>
 #include <reset.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/mrc_cache.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c
index 41c0b1c312..d1f2e49aff 100644
--- a/src/soc/intel/common/fsp_ramstage.c
+++ b/src/soc/intel/common/fsp_ramstage.c
@@ -22,7 +22,7 @@
 #include <cbmem.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h>
 #include <soc/intel/common/memmap.h>
 #include <soc/intel/common/ramstage.h>
diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c
index ddf567591d..bdb23e2b64 100644
--- a/src/soc/intel/common/raminit.c
+++ b/src/soc/intel/common/raminit.c
@@ -19,7 +19,7 @@
 
 #include <cbmem.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h> /* hexdump */
 #include <reset.h>
 #include <soc/intel/common/memmap.h>
diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h
index 414142a8ae..d6cb895174 100644
--- a/src/soc/intel/common/ramstage.h
+++ b/src/soc/intel/common/ramstage.h
@@ -21,7 +21,7 @@
 #ifndef _INTEL_COMMON_RAMSTAGE_H_
 #define _INTEL_COMMON_RAMSTAGE_H_
 
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/util.h>
 #include <stdint.h>
 
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
index 440cad75f5..b35ff6652a 100644
--- a/src/soc/intel/common/romstage.h
+++ b/src/soc/intel/common/romstage.h
@@ -24,7 +24,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <memory_info.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/util.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>		/* chip_power_state */
diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c
index 0e46b70977..b12ec04712 100644
--- a/src/soc/intel/common/vbt.c
+++ b/src/soc/intel/common/vbt.c
@@ -20,7 +20,7 @@
 
 #include <cbfs.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h>
 #include <soc/intel/common/ramstage.h>
 #include <string.h>
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 32ecb5d60b..38668da4b1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -61,19 +61,12 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
-CPPFLAGS_common += -I$(src)/arch/x86/include/
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 
+# Currently used for microcode path.
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 2c498838b5..afb0ff6b70 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -23,7 +23,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <string.h>
diff --git a/src/soc/intel/skylake/include/soc/chipset_fsp_util.h b/src/soc/intel/skylake/include/soc/chipset_fsp_util.h
deleted file mode 100644
index 2c05f01b79..0000000000
--- a/src/soc/intel/skylake/include/soc/chipset_fsp_util.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CHIPSET_FSP_UTIL_H_
-#define _CHIPSET_FSP_UTIL_H_
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h>				/* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h>		/* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h>	/* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h>	/* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>	/* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>	/* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>	/* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h>		/* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h>	/* HOB routine declarations */
-#include <FspUpdVpd.h>		/* Vital/updatable product data definitions */
-
-#endif	/* _CHIPSET_FSP_UTIL_H_ */
diff --git a/src/soc/intel/skylake/ramstage.c b/src/soc/intel/skylake/ramstage.c
index 51e9b31d65..3646843e87 100644
--- a/src/soc/intel/skylake/ramstage.c
+++ b/src/soc/intel/skylake/ramstage.c
@@ -18,9 +18,6 @@
  * Foundation, Inc.
  */
 
-#include <bootstate.h>
-#include <console/console.h>
-#include <fsp_util.h>
 #include <soc/ramstage.h>
 #include <soc/intel/common/ramstage.h>