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authorSubrata Banik <subrata.banik@intel.com>2018-10-06 13:24:14 +0530
committerDuncan Laurie <dlaurie@chromium.org>2018-10-09 20:11:00 +0000
commit7cf9862657977ad7d7be2ff28c3f227faf611a2f (patch)
treefbbac66cf0288ce173a4582f35abc61c32ffbbb3 /src/soc/intel
parent819b143925bc060b09ccb39b9a9395fd09f1b014 (diff)
downloadcoreboot-7cf9862657977ad7d7be2ff28c3f227faf611a2f.tar.xz
soc/intel/cannonlake: Disable Legacy PME for Root ports
Legacy PME are enabled by default in FSP-S UPD. This policy sets PME Interrupt Enable (PIE) bit of RCTL register to trigger interrupt generation when RSTS.PS state has changed (either due to 0->1 transition or due to this bit being set with RSTS.PS already set). Due to this interrupt generation, system wakes from sleep immediately it enters. This patch overrides root port legacy pme upd policy from coreboot to ensure no false SCI is triggerd when system is in S3/S0ix state. BUG=b:113083354 BRANCH=none TEST=Able to make S3 resume using wake on wifi connect/disconnect usecase without any failure. Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 9befdc8fda..6167346f89 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -128,6 +128,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* S0ix */
params->PchPmSlpS0Enable = config->s0ix_enable;
+ /* disable Legacy PME */
+ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;