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authorDuncan Laurie <dlaurie@chromium.org>2018-05-07 11:56:52 -0700
committerDuncan Laurie <dlaurie@chromium.org>2018-05-08 14:40:23 +0000
commit8735d1bdc7ff76ee643472012af026e92d82477a (patch)
tree8a390a43e9419badb06a136fc689bfcb35c33da5 /src/soc/intel
parent3e582d1613c9df08b0a0a745cd720bd397b0cf49 (diff)
downloadcoreboot-8735d1bdc7ff76ee643472012af026e92d82477a.tar.xz
soc/intel/skylake: Support PCH UART 0 and 1 for console
The current PCH UART support for console is limited to UART2. This change adds support for specifying UART0 or UART1 to be used instead by changing CONFIG_UART_FOR_CONSOLE in the board level Kconfig. The default is still 2. This is tested with a board that uses UART0 for debug output. Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/26140 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/uart.c35
1 files changed, 27 insertions, 8 deletions
diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c
index 6f3c21e586..1b4e96eb60 100644
--- a/src/soc/intel/skylake/uart.c
+++ b/src/soc/intel/skylake/uart.c
@@ -31,10 +31,20 @@
#define PCR_SERIAL_IO_GPPRVRW7 0x618
#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
-/* UART2 pad configuration. Support RXD and TXD for now. */
-static const struct pad_config uart2_pads[] = {
-/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+/* UART pad configuration. Support RXD and TXD for now. */
+static const struct pad_config uart_pads[][2] = {
+ {
+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */
+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */
+ },
+ {
+ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */
+ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */
+ },
+ {
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */
+ }
};
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
@@ -50,9 +60,9 @@ void pch_uart_init(void)
{
uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
- uart_common_init(PCH_DEV_UART2, base);
+ uart_common_init(pch_uart_get_debug_controller(), base);
- /* Put UART2 in byte access mode for 16550 compatibility */
+ /* Put UART in byte access mode for 16550 compatibility */
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
@@ -64,7 +74,8 @@ void pch_uart_init(void)
lpss_clk_read(base);
}
- gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ gpio_configure_pads(uart_pads[CONFIG_UART_FOR_CONSOLE],
+ ARRAY_SIZE(uart_pads[CONFIG_UART_FOR_CONSOLE]));
}
#if !ENV_SMM
@@ -96,5 +107,13 @@ bool pch_uart_init_debug_controller_on_resume(void)
device_t pch_uart_get_debug_controller(void)
{
- return PCH_DEV_UART2;
+ switch (CONFIG_UART_FOR_CONSOLE) {
+ case 0:
+ return PCH_DEV_UART0;
+ case 1:
+ return PCH_DEV_UART1;
+ case 2:
+ default:
+ return PCH_DEV_UART2;
+ }
}