diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-11-30 17:58:38 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-12-02 16:39:55 +0100 |
| commit | 89e39b5c55cd7612c70cb25d2b2000965cc25539 (patch) | |
| tree | 86dffb03b8280f1eb34ea66a2bee4f041dc00ad2 /src/soc/intel | |
| parent | 3b637531c91d0cb290dcff26584274f41c06ec85 (diff) | |
| download | coreboot-89e39b5c55cd7612c70cb25d2b2000965cc25539.tar.xz | |
soc/intel/apollolake: Drop privilege level to IA_UNTRUSTED
As per guidelines CPU security level should be dropped before OS start,
so that certain MSRs are locked out. Drop privilege levels on all logical
CPUs.
BUG=chrome-os-partner:60454
TEST=iotools rdmsr x 0x120, make sure bit 6 is set, rdmsr x 0x121 results
in io error.
Change-Id: I67540f6da16f58b822db9160d00b7a5e235188db
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17665
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/car.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/cpu.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/cpu.h | 2 |
3 files changed, 12 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 68bcb31eb1..d58dc0a403 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -28,7 +28,7 @@ static void flush_l1d_to_l2(void) { msr_t msr = rdmsr(MSR_POWER_MISC); - msr.lo |= (1 << 8); + msr.lo |= FLUSH_DL1_L2; wrmsr(MSR_POWER_MISC, msr); } diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 949736821e..8b8f963e4c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -53,6 +53,13 @@ static const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; +static void enable_untrusted_mode(void) +{ + msr_t msr = rdmsr(MSR_POWER_MISC); + msr.lo |= ENABLE_IA_UNTRUSTED; + wrmsr(MSR_POWER_MISC, msr); +} + static void soc_core_init(device_t cpu) { /* Set core MSRs */ @@ -63,6 +70,8 @@ static void soc_core_init(device_t cpu) * implemented in microcode. */ enable_pm_timer_emulation(); + /* Drop privilege level */ + enable_untrusted_mode(); } static struct device_operations cpu_dev_ops = { diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 38ce4ff913..db9d3dde05 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -31,6 +31,8 @@ void set_max_freq(void); #define MSR_PLATFORM_INFO 0xce #define MSR_POWER_MISC 0x120 +#define ENABLE_IA_UNTRUSTED (1 << 6) +#define FLUSH_DL1_L2 (1 << 8) #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_EVICT_CTL 0x2e0 #define MSR_EMULATE_PM_TMR 0x121 |