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authorAaron Durbin <adurbin@chromium.org>2014-03-19 11:48:33 -0500
committerMarc Jones <marc.jones@se-eng.com>2014-10-28 17:56:36 +0100
commit89f5292ee63cb6f387c06bfbdb4343cc675bc938 (patch)
tree66feefb89d8292ac9381836c123494622a058e78 /src/soc/intel
parent565d409753a9878fef19eedc4a916d1efc3026a0 (diff)
downloadcoreboot-89f5292ee63cb6f387c06bfbdb4343cc675bc938.tar.xz
baytrail: move cache-as-ram base address to 0xfe000000
Moving the cache-as-ram base address to 0xfe000000 will provide more breathing room in the physical address space. It will also allow for larger SPI roms in the future. BUG=chrome-os-partner:27045 BRANCH=baytrail CQ-DEPEND=CL:*157278 TEST=Built and booted. Suspended and resumes. Vboot works, MRC settings are being saved as well. Change-Id: I618c069e504f545e02de5ac54e057566f0b5d6c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190700 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 73c07a319d678f3e9be2fac64599c94f91c9ad9c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7212 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/baytrail/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 3669c30f54..bc90b11d73 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -113,7 +113,7 @@ endif # HAVE_MRC
config DCACHE_RAM_BASE
hex
- default 0xff800000
+ default 0xfe000000
config DCACHE_RAM_SIZE
hex