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authorAaron Durbin <adurbin@chromium.org>2013-11-14 11:06:17 -0600
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-07 12:05:58 +0200
commit99d8818af332f4db8ded058c7e5e59e2f56f7bc9 (patch)
tree48c35e247568bc199c30d9d230e341affe49c9a3 /src/soc/intel
parent281abfb2dbf138bd732404f4412d8c6bee611bee (diff)
downloadcoreboot-99d8818af332f4db8ded058c7e5e59e2f56f7bc9.tar.xz
baytrail: don't allow PCIE wake ups
The PCIe subsystem was constantly waking up boards from S3 and S5. Completely disable PCIe wake ups. It can be made mainboard-configurable later if needed. BUG=chrome-os-partner:24004 BRANCH=None TEST=Both S3 and EC RW->RW update (trip through S5) don't cause wakeups. Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176791 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4972 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/baytrail/smm.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index c654c8597e..e10c70b699 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -93,8 +93,8 @@ void southcluster_smm_enable_smi(void)
{
printk(BIOS_DEBUG, "Enabling SMIs.\n");
- /* Configure events */
- enable_pm1(PWRBTN_EN | GBL_EN);
+ /* Configure events Disable pcie wake. */
+ enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
disable_gpe(PME_B0_EN);
/* Set up the GPIO route. */