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authorAaron Durbin <adurbin@chromium.org>2013-10-11 00:44:06 -0500
committerAaron Durbin <adurbin@google.com>2014-02-16 20:37:03 +0100
commit9d9d7f04296e2c6de5bd10ee4bff1a496006f9e1 (patch)
tree2042e72caa55e408d5ab23f232449d9b744b1040 /src/soc/intel
parent6f6a249a75927476ba5e06bb2b0a0138e0cf63ea (diff)
downloadcoreboot-9d9d7f04296e2c6de5bd10ee4bff1a496006f9e1.tar.xz
baytrail: fix tsc rate
Despite some references to a fixed bclk in some of the docs the bclk is variable per sku. Therefore, perform the calculation according to the BSEL_CR_OVERCLOCK_CONTROL msr which provides the bclk for the cpu cores in Bay Trail. BUG=chrome-os-partner:23166 BRANCH=None TEST=Built and booted B3. correctly says: clocks_per_usec: 2133 Change-Id: I55da45d42e7672fdb3b821c8aed7340a6f73dd08 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172771 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4883 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/baytrail/baytrail/msr.h1
-rw-r--r--src/soc/intel/baytrail/tsc_freq.c21
2 files changed, 19 insertions, 3 deletions
diff --git a/src/soc/intel/baytrail/baytrail/msr.h b/src/soc/intel/baytrail/baytrail/msr.h
index 7f3b3b26fd..5094f965c7 100644
--- a/src/soc/intel/baytrail/baytrail/msr.h
+++ b/src/soc/intel/baytrail/baytrail/msr.h
@@ -21,6 +21,7 @@
#define _BAYTRAIL_MSR_H_
#define MSR_IA32_PLATFORM_ID 0x17
+#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd
#define MSR_PLATFORM_INFO 0xce
#define MSR_IA32_PERF_CTL 0x199
#define MSR_IA32_MISC_ENABLES 0x1a0
diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c
index 0cf7273b74..e4327318da 100644
--- a/src/soc/intel/baytrail/tsc_freq.c
+++ b/src/soc/intel/baytrail/tsc_freq.c
@@ -27,14 +27,29 @@
#include <baytrail/romstage.h>
#endif
-
-#define BCLK 100 /* 100 MHz */
unsigned long tsc_freq_mhz(void)
{
msr_t platform_info;
+ msr_t clk_info;
+ unsigned long bclk_khz;
platform_info = rdmsr(MSR_PLATFORM_INFO);
- return BCLK * ((platform_info.lo >> 8) & 0xff);
+ clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
+ switch (clk_info.lo & 0x3) {
+ case 0:
+ bclk_khz = 83333;
+ break;
+ case 1:
+ bclk_khz = 100000;
+ break;
+ case 2:
+ bclk_khz = 133333;
+ break;
+ case 3:
+ bclk_khz = 116666;
+ break;
+ }
+ return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
}
void set_max_freq(void)