summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorJohn Zhao <john.zhao@intel.com>2020-03-03 10:03:57 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-06 07:52:45 +0000
commitad64781dee9cf513b60d72c0d3ec1c67bac7362d (patch)
treed672e3b156b15afdd6ca61b68a5e42e473b8198c /src/soc/intel
parent17dda3adb3850bdebc94aca693405e753f6910ab (diff)
downloadcoreboot-ad64781dee9cf513b60d72c0d3ec1c67bac7362d.tar.xz
soc/intel/tigerlake: Avoid NULL pointer dereference
Coverity detects pointer dev as FORWARD_NULL. Add sanity check for dev to prevent NULL pointer dereference. BUG=CID 1353148 TEST=Built and boot up to kernel. Change-Id: Ic0ad1ec79c950a3c17feccdde4f87f4a107fe8c0 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/tigerlake/fsp_params_jsl.c11
-rw-r--r--src/soc/intel/tigerlake/fsp_params_tgl.c10
2 files changed, 15 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c
index 8eb3fbacaf..6cb3b6718d 100644
--- a/src/soc/intel/tigerlake/fsp_params_jsl.c
+++ b/src/soc/intel/tigerlake/fsp_params_jsl.c
@@ -158,9 +158,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
- if (!dev || !xdci_can_enable())
- dev->enabled = 0;
- params->XdciEnable = dev->enabled;
+ if (dev) {
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+
+ params->XdciEnable = dev->enabled;
+ } else {
+ params->XdciEnable = 0;
+ }
/* Provide correct UART number for FSP debug logs */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 0587b88868..9e22b58e7c 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -115,9 +115,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
- if (!xdci_can_enable())
- dev->enabled = 0;
- params->XdciEnable = dev->enabled;
+ if (dev) {
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+ params->XdciEnable = dev->enabled;
+ } else {
+ params->XdciEnable = 0;
+ }
/* PCH UART selection for FSP Debug */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;