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authorJohn Zhao <john.zhao@intel.com>2018-10-25 10:45:19 -0700
committerFurquan Shaikh <furquan@google.com>2018-10-31 05:38:42 +0000
commitb3c27f0a242491d96e772cac356e845331c9f45a (patch)
tree009855e4df6faa47fc63a223a8aca49020dc84e1 /src/soc/intel
parent2257a35862576b36e89d8f16fb8765913cb06389 (diff)
downloadcoreboot-b3c27f0a242491d96e772cac356e845331c9f45a.tar.xz
soc/intel/apollolake: Revert the w/a nWR_24 setting
GLK FSP 2.0.6.0 has properly determined MR1 value during InitializeJedec. Revert the w/a code "odt_config |= nWR_24" in coreboot. BUG=b:118422998 CQ-DEPEND=CL:*703187 TEST=Verified booting to kernel. Change-Id: I6dd3c14b2048259a5518e1f72ff1061b9c5c7dfe Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/meminit.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 9e6622cc1b..889bbde66d 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -69,7 +69,7 @@ size_t iohole_in_mib(void)
return 2 * (GiB / MiB);
}
-static void set_lpddr4_defaults(FSP_M_CONFIG *cfg, int speed)
+static void set_lpddr4_defaults(FSP_M_CONFIG *cfg)
{
uint8_t odt_config;
@@ -126,10 +126,6 @@ static void set_lpddr4_defaults(FSP_M_CONFIG *cfg, int speed)
up to 1.1V. */
odt_config = ODT_A_B_HIGH_HIGH;
- /* Need to set correct Write-Recovery configuration based on speed. */
- if (IS_ENABLED(CONFIG_SOC_INTEL_GLK) && speed >= LP4_SPEED_2133)
- odt_config |= nWR_24;
-
cfg->Ch0_OdtConfig = odt_config;
cfg->Ch1_OdtConfig = odt_config;
cfg->Ch2_OdtConfig = odt_config;
@@ -213,7 +209,7 @@ void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed)
printk(BIOS_INFO, "LP4DDR speed is %dMHz\n", speed);
cfg->Profile = fsp_memory_profile(speed);
- set_lpddr4_defaults(cfg, speed);
+ set_lpddr4_defaults(cfg);
}
static void enable_logical_chan0(FSP_M_CONFIG *cfg,