soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock

List of changes:
1. Add required SoC programming till bootblock
2. Include only required headers into include/soc
3. Add CPU/PCH/SA EDS document number and chapter number
4. Include ADL-P related DID, BDF

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I204e692fabb84fce297bebee465f4ca624c6fe56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

15 files changed, 1136 insertions, 0 deletions

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
new file mode 100644
index 0000000000..ee1e871ebb
--- /dev/null
+++ b/src/soc/intel/alderlake/Kconfig
@@ -0,0 +1,132 @@
+config SOC_INTEL_ALDERLAKE
+	bool
+	help
+	  Intel Alderlake support
+
+if SOC_INTEL_ALDERLAKE
+
+config CPU_SPECIFIC_OPTIONS
+	def_bool y
+	select ARCH_BOOTBLOCK_X86_32
+	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
+	select BOOT_DEVICE_SUPPORTS_WRITES
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
+	select IDT_IN_EVERY_STAGE
+	select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
+	select MICROCODE_BLOB_UNDISCLOSED
+	select SOC_INTEL_COMMON
+	select SOC_INTEL_COMMON_BLOCK
+	select SOC_INTEL_COMMON_BLOCK_CPU
+	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
+	select SOC_INTEL_COMMON_BLOCK_SA
+	select SOC_INTEL_COMMON_PCH_BASE
+	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_COMMON_BLOCK_CAR
+	select SSE2
+	select SUPPORT_CPU_UCODE_IN_CBFS
+	select TSC_MONOTONIC_TIMER
+	select UDELAY_TSC
+
+config DCACHE_RAM_BASE
+	default 0xfef00000
+
+config DCACHE_RAM_SIZE
+	default 0x80000
+	help
+	  The size of the cache-as-ram region required during bootblock
+	  and/or romstage.
+
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x40400
+	help
+	  The amount of anticipated stack usage in CAR by bootblock and
+	  other stages. In the case of FSP_USES_CB_STACK default value will be
+	  sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement
+	  (~1KiB).
+
+config FSP_TEMP_RAM_SIZE
+	hex
+	default 0x20000
+	help
+	  The amount of anticipated heap usage in CAR by FSP.
+	  Refer to Platform FSP integration guide document to know
+	  the exact FSP requirement for Heap setup.
+
+config IFD_CHIPSET
+	string
+	default "adl"
+
+config IED_REGION_SIZE
+	hex
+	default 0x400000
+
+config HEAP_SIZE
+	hex
+	default 0x10000
+
+config PCR_BASE_ADDRESS
+	hex
+	default 0xfd000000
+	help
+	  This option allows you to select MMIO Base Address of sideband bus.
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xc0000000
+
+config CPU_BCLK_MHZ
+	int
+	default 100
+
+config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
+	int
+	default 120
+
+config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
+	int
+	default 133
+
+config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
+	int
+	default 7
+
+config SOC_INTEL_I2C_DEV_MAX
+	int
+	default 6
+
+config SOC_INTEL_UART_DEV_MAX
+	int
+	default 7
+
+config CONSOLE_UART_BASE_ADDRESS
+	hex
+	default 0xfe032000
+	depends on INTEL_LPSS_UART_FOR_CONSOLE
+
+# Clock divider parameters for 115200 baud rate
+# Baudrate = (UART source clcok * M) /(N *16)
+# ADL UART source clock: 120MHz
+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
+	hex
+	default 0x25a
+
+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
+	hex
+	default 0x7fff
+
+config CHROMEOS
+	select CHROMEOS_RAMOOPS_DYNAMIC
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0xC000
+
+config CBFS_SIZE
+	hex
+	default 0x200000
+
+config PRERAM_CBMEM_CONSOLE_SIZE
+	hex
+	default 0x1400
+endif
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
new file mode 100644
index 0000000000..cc37b6fd00
--- /dev/null
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -0,0 +1,8 @@
+ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y)
+bootblock-y += bootblock/bootblock.c
+bootblock-y += bootblock/cpu.c
+bootblock-y += bootblock/pch.c
+bootblock-y += bootblock/report_platform.c
+CPPFLAGS_common += -I$(src)/soc/intel/alderlake
+CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include
+endif
diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c
new file mode 100644
index 0000000000..e7d97c50bf
--- /dev/null
+++ b/src/soc/intel/alderlake/bootblock/bootblock.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <intelblocks/systemagent.h>
+#include <intelblocks/tco.h>
+#include <intelblocks/uart.h>
+#include <soc/bootblock.h>
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+	/* Call lib/bootblock.c main */
+	bootblock_main_with_basetime(base_timestamp);
+}
+
+void bootblock_soc_early_init(void)
+{
+	bootblock_systemagent_early_init();
+	bootblock_pch_early_init();
+	bootblock_cpu_init();
+	pch_early_iorange_init();
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+		uart_bootblock_init();
+}
+
+void bootblock_soc_init(void)
+{
+	report_platform_info();
+	pch_init();
+
+	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
+	tco_configure();
+}
diff --git a/src/soc/intel/alderlake/bootblock/cpu.c b/src/soc/intel/alderlake/bootblock/cpu.c
new file mode 100644
index 0000000000..4225358de5
--- /dev/null
+++ b/src/soc/intel/alderlake/bootblock/cpu.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Alder Lake Processor PCH Datasheet
+ * Document number: 621483
+ * Chapter number: 7
+ */
+
+#include <intelblocks/fast_spi.h>
+#include <soc/bootblock.h>
+
+void bootblock_cpu_init(void)
+{
+	/*
+	 * Alderlake platform doesn't support booting from any other media
+	 * than SPI flash and on IA platform SPI is memory mapped hence
+	 * enabling temporary caching of memory-mapped spi boot media.
+	 */
+	fast_spi_cache_bios_region();
+}
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c
new file mode 100644
index 0000000000..8452d83290
--- /dev/null
+++ b/src/soc/intel/alderlake/bootblock/pch.c
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Alder Lake Processor PCH Datasheet
+ * Document number: 621483
+ * Chapter number: 2, 3, 4, 27, 28
+ */
+
+#include <device/mmio.h>
+#include <device/device.h>
+#include <device/pci_ops.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/p2sb.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/rtc.h>
+#include <soc/bootblock.h>
+#include <soc/espi.h>
+#include <soc/iomap.h>
+#include <soc/p2sb.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE       0x1100
+#define PCR_PSFX_TO_SHDW_BAR0               0
+#define PCR_PSFX_TO_SHDW_BAR1               0x4
+#define PCR_PSFX_TO_SHDW_BAR2               0x8
+#define PCR_PSFX_TO_SHDW_BAR3               0xC
+#define PCR_PSFX_TO_SHDW_BAR4               0x10
+#define PCR_PSFX_TO_SHDW_PCIEN_IOEN         0x01
+#define PCR_PSFX_T0_SHDW_PCIEN              0x1C
+
+#define PCR_DMI_DMICTL                      0x2234
+#define  PCR_DMI_DMICTL_SRLOCK              (1 << 31)
+
+#define PCR_DMI_ACPIBA                      0x27B4
+#define PCR_DMI_ACPIBDID                    0x27B8
+#define PCR_DMI_PMBASEA                     0x27AC
+#define PCR_DMI_PMBASEC                     0x27B0
+
+#define PCR_DMI_LPCIOD                      0x2770
+#define PCR_DMI_LPCIOE                      0x2774
+
+static void soc_config_pwrmbase(void)
+{
+	/*
+	 * Assign Resources to PWRMBASE
+	 * Clear BIT 1-2 Command Register
+	 */
+	pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
+
+	/* Program PWRM Base */
+	pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
+
+	/* Enable Bus Master and MMIO Space */
+	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
+
+	/* Enable PWRM in PMC */
+	setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
+}
+
+void bootblock_pch_early_init(void)
+{
+	fast_spi_early_init(SPI_BASE_ADDRESS);
+	gspi_early_bar_init();
+	p2sb_enable_bar();
+	p2sb_configure_hpet();
+
+	/*
+	 * Enabling PWRM Base for accessing
+	 * Global Reset Cause Register.
+	 */
+	soc_config_pwrmbase();
+}
+
+static void soc_config_acpibase(void)
+{
+	uint32_t pmc_reg_value;
+	uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE;
+
+	pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
+
+	if (pmc_reg_value != 0xffffffff) {
+		/* Disable Io Space before changing the address */
+		pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
+				~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
+		/* Program ABASE in PSF3 PMC space BAR4*/
+		pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
+				ACPI_BASE_ADDRESS);
+		/* Enable IO Space */
+		pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
+				~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
+	}
+}
+
+static int pch_check_decode_enable(void)
+{
+	const uint32_t dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
+
+	/*
+	 * This cycle decoding is only allowed to set when
+	 * DMICTL.SRLOCK is 0.
+	 */
+	if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
+		return -1;
+	return 0;
+}
+
+void pch_early_iorange_init(void)
+{
+	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+		LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
+
+	/* IO Decode Range */
+	if (CONFIG(DRIVERS_UART_8250IO))
+		lpc_io_setup_comm_a_b();
+
+	/* IO Decode Enable */
+	if (pch_check_decode_enable() == 0) {
+		io_enables = lpc_enable_fixed_io_ranges(io_enables);
+		/*
+		 * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
+		 * value programmed in ESPI PCI offset 82h.
+		 */
+		pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+		/*
+		 * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
+		 * value programmed in LPC PCI offset 80h.
+		 */
+		pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
+	}
+
+	/* Program generic IO Decode Range */
+	pch_enable_lpc();
+}
+
+void pch_init(void)
+{
+	/*
+	 * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
+	 * GPE0_STS, GPE0_EN registers.
+	 */
+	soc_config_acpibase();
+
+	/* Set up GPE configuration */
+	pmc_gpe_init();
+
+	enable_rtc_upper_bank();
+}
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
new file mode 100644
index 0000000000..38e909c73d
--- /dev/null
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Alder Lake Platform Stepping and IDs
+ * Document number: 619362, 619501
+ * Chapter number: 2, 14
+ */
+
+#include <arch/cpu.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/name.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelblocks/mp_init.h>
+#include <soc/bootblock.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <string.h>
+
+static struct {
+	u32 cpuid;
+	const char *name;
+} cpu_table[] = {
+	{ CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" },
+};
+
+static struct {
+	u16 mchid;
+	const char *name;
+} mch_table[] = {
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, "Alderlake-P" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_2, "Alderlake-P" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, "Alderlake-P" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, "Alderlake-P" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, "Alderlake-P" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, "Alderlake-P" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, "Alderlake-P" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_8, "Alderlake-P" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_9, "Alderlake-P" },
+};
+
+static struct {
+	u16 espiid;
+	const char *name;
+} pch_table[] = {
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" },
+	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" },
+};
+
+static struct {
+	u16 igdid;
+	const char *name;
+} igd_table[] = {
+	{ PCI_DEVICE_ID_INTEL_ADL_GT0, "Alderlake GT0" },
+	{ PCI_DEVICE_ID_INTEL_ADL_GT1, "Alderlake GT1" },
+	{ PCI_DEVICE_ID_INTEL_ADL_GT1_1, "Alderlake GT1" },
+	{ PCI_DEVICE_ID_INTEL_ADL_GT1_2, "Alderlake GT1" },
+	{ PCI_DEVICE_ID_INTEL_ADL_GT1_3, "Alderlake GT1" },
+	{ PCI_DEVICE_ID_INTEL_ADL_GT1_4, "Alderlake GT1" },
+	{ PCI_DEVICE_ID_INTEL_ADL_GT1_5, "Alderlake GT1" },
+	{ PCI_DEVICE_ID_INTEL_ADL_GT1_6, "Alderlake GT1" },
+	{ PCI_DEVICE_ID_INTEL_ADL_GT1_7, "Alderlake GT1" },
+	{ PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" },
+	{ PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" },
+};
+
+static inline uint8_t get_dev_revision(pci_devfn_t dev)
+{
+	return pci_read_config8(dev, PCI_REVISION_ID);
+}
+
+static inline uint16_t get_dev_id(pci_devfn_t dev)
+{
+	return pci_read_config16(dev, PCI_DEVICE_ID);
+}
+
+static void report_cpu_info(void)
+{
+	u32 i, cpu_id, cpu_feature_flag;
+	char cpu_name[49];
+	int vt, txt, aes;
+	static const char *const mode[] = {"NOT ", ""};
+	const char *cpu_type = "Unknown";
+
+	fill_processor_name(cpu_name);
+	cpu_id = cpu_get_cpuid();
+
+	/* Look for string to match the name */
+	for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
+		if (cpu_table[i].cpuid == cpu_id) {
+			cpu_type = cpu_table[i].name;
+			break;
+		}
+	}
+
+	printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
+	printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
+	       cpu_id, cpu_type, get_current_microcode_rev());
+
+	cpu_feature_flag = cpu_get_feature_flags_ecx();
+	aes = !!(cpu_feature_flag & CPUID_AES);
+	txt = !!(cpu_feature_flag & CPUID_SMX);
+	vt = !!(cpu_feature_flag & CPUID_VMX);
+	printk(BIOS_DEBUG,
+		"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
+		mode[aes], mode[txt], mode[vt]);
+}
+
+static void report_mch_info(void)
+{
+	int i;
+	uint16_t mchid = get_dev_id(SA_DEV_ROOT);
+	const char *mch_type = "Unknown";
+
+	for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
+		if (mch_table[i].mchid == mchid) {
+			mch_type = mch_table[i].name;
+			break;
+		}
+	}
+
+	printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
+		mchid, get_dev_revision(SA_DEV_ROOT), mch_type);
+}
+
+static void report_pch_info(void)
+{
+	int i;
+	pci_devfn_t dev = PCH_DEV_ESPI;
+	uint16_t espiid = get_dev_id(dev);
+	const char *pch_type = "Unknown";
+
+	for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+		if (pch_table[i].espiid == espiid) {
+			pch_type = pch_table[i].name;
+			break;
+		}
+	}
+	printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
+		espiid, get_dev_revision(dev), pch_type);
+}
+
+static void report_igd_info(void)
+{
+	int i;
+	pci_devfn_t dev = SA_DEV_IGD;
+	uint16_t igdid = get_dev_id(dev);
+	const char *igd_type = "Unknown";
+
+	for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
+		if (igd_table[i].igdid == igdid) {
+			igd_type = igd_table[i].name;
+			break;
+		}
+	}
+	printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
+		igdid, get_dev_revision(dev), igd_type);
+}
+
+void report_platform_info(void)
+{
+	report_cpu_info();
+	report_mch_info();
+	report_pch_info();
+	report_igd_info();
+}
diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h
new file mode 100644
index 0000000000..9816b317db
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/bootblock.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ALDERLAKE_BOOTBLOCK_H_
+#define _SOC_ALDERLAKE_BOOTBLOCK_H_
+
+/* Bootblock pre console init programming */
+void bootblock_cpu_init(void);
+void bootblock_pch_early_init(void);
+
+/* Bootblock post console init programming */
+void pch_init(void);
+void pch_early_iorange_init(void);
+void report_platform_info(void);
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/espi.h b/src/soc/intel/alderlake/include/soc/espi.h
new file mode 100644
index 0000000000..49ccdb4f9d
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/espi.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Alder Lake Processor PCH Datasheet
+ * Document number: 621483
+ * Chapter number: 2
+ */
+
+#ifndef _SOC_ALDERLAKE_ESPI_H_
+#define _SOC_ALDERLAKE_ESPI_H_
+
+/* PCI Configuration Space (D31:F0): ESPI */
+#define SCI_IRQ_SEL		(7 << 0)
+#define SCIS_IRQ9		0
+#define SCIS_IRQ10		1
+#define SCIS_IRQ11		2
+#define SCIS_IRQ20		4
+#define SCIS_IRQ21		5
+#define SCIS_IRQ22		6
+#define SCIS_IRQ23		7
+#define SERIRQ_CNTL		0x64
+#define ESPI_IO_DEC		0x80 /* IO Decode Ranges Register */
+#define   COMA_RANGE		0x0 /* 0x3F8 - 0x3FF COM1*/
+#define   COMB_RANGE		0x1 /* 0x2F8 - 0x2FF COM2*/
+#define ESPI_GEN1_DEC		0x84 /* ESPI IF Generic Decode Range 1 */
+#define ESPI_GEN2_DEC		0x88 /* ESPI IF Generic Decode Range 2 */
+#define ESPI_GEN3_DEC		0x8c /* ESPI IF Generic Decode Range 3 */
+#define ESPI_GEN4_DEC		0x90 /* ESPI IF Generic Decode Range 4 */
+#define LGMR			0x98 /* ESPI Generic Memory Range */
+#define PCCTL			0xE0 /* PCI Clock Control */
+#define   CLKRUN_EN		(1 << 0)
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h
new file mode 100644
index 0000000000..e71ddb58ac
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/iomap.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Alder Lake Firmware Architecture Specification
+ * Document number: 626540
+ * Chapter number: 4
+ */
+
+#ifndef _SOC_ALDERLAKE_IOMAP_H_
+#define _SOC_ALDERLAKE_IOMAP_H_
+
+/*
+ * Memory-mapped I/O registers.
+ */
+#define MCFG_BASE_ADDRESS	CONFIG_MMCONF_BASE_ADDRESS
+#define MCFG_BASE_SIZE		0x4000000
+
+#define PCH_PRESERVED_BASE_ADDRESS	0xfc800000
+#define PCH_PRESERVED_BASE_SIZE	0x02000000
+
+#define PCH_TRACE_HUB_BASE_ADDRESS	0xfc800000
+#define PCH_TRACE_HUB_BASE_SIZE	0x00800000
+
+#define UART_BASE_SIZE		0x1000
+
+#define UART_BASE_0_ADDRESS	0xfe03e000
+/* Both UART BAR 0 and 1 are 4KB in size */
+#define UART_BASE_0_ADDR(x)	(UART_BASE_0_ADDRESS + (2 * \
+					UART_BASE_SIZE * (x)))
+#define UART_BASE(x)		UART_BASE_0_ADDR(x)
+
+#define DMI_BASE_ADDRESS	0xfeda0000
+#define DMI_BASE_SIZE		0x1000
+
+#define EP_BASE_ADDRESS		0xfeda1000
+#define EP_BASE_SIZE		0x1000
+
+#define EDRAM_BASE_ADDRESS	0xfed80000
+#define EDRAM_BASE_SIZE		0x4000
+
+#define REG_BASE_ADDRESS	0xfb000000
+#define REG_BASE_SIZE		0x1000
+
+#define HPET_BASE_ADDRESS	0xfed00000
+
+#define PCH_PWRM_BASE_ADDRESS	0xfe000000
+#define PCH_PWRM_BASE_SIZE	0x10000
+
+#define SPI_BASE_ADDRESS	0xfe010000
+
+#define GPIO_BASE_SIZE		0x10000
+
+#define HECI1_BASE_ADDRESS	0xfeda2000
+
+#define VTD_BASE_ADDRESS	0xfed90000
+#define VTD_BASE_SIZE		0x00004000
+
+#define MCH_BASE_ADDRESS	0xfedc0000
+#define MCH_BASE_SIZE		0x20000
+
+#define EARLY_GSPI_BASE_ADDRESS 0xfe030000
+
+#define EARLY_I2C_BASE_ADDRESS	0xfe020000
+#define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
+
+#define IOM_BASE_ADDRESS	0xfbc10000
+#define IOM_BASE_SIZE		0x1600
+
+/*
+ * I/O port address space
+ */
+#define SMBUS_BASE_ADDRESS	0x0efa0
+#define SMBUS_BASE_SIZE		0x20
+
+#define ACPI_BASE_ADDRESS	0x1800
+#define ACPI_BASE_SIZE		0x100
+
+#define TCO_BASE_ADDRESS	0x400
+#define TCO_BASE_SIZE		0x20
+
+#define P2SB_BAR		CONFIG_PCR_BASE_ADDRESS
+#define P2SB_SIZE		(16 * MiB)
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/p2sb.h b/src/soc/intel/alderlake/include/soc/p2sb.h
new file mode 100644
index 0000000000..27268511a5
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/p2sb.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Alder Lake Processor PCH Datasheet
+ * Document number: 621483
+ * Chapter number: 3
+ */
+
+#ifndef _SOC_ALDERLAKE_P2SB_H_
+#define _SOC_ALDERLAKE_P2SB_H_
+
+#define HPTC_OFFSET			0x60
+#define HPTC_ADDR_ENABLE_BIT		(1 << 7)
+
+#define PCH_P2SB_EPMASK0		0x220
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/pch.h b/src/soc/intel/alderlake/include/soc/pch.h
new file mode 100644
index 0000000000..89e8a8a1f7
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/pch.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ALDERLAKE_PCH_H_
+#define _SOC_ALDERLAKE_PCH_H_
+
+#define PCIE_CLK_NOTUSED		0xFF
+#define PCIE_CLK_LAN			0x70
+#define PCIE_CLK_FREE			0x80
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
new file mode 100644
index 0000000000..eedcc27185
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ALDERLAKE_PCI_DEVS_H_
+#define _SOC_ALDERLAKE_PCI_DEVS_H_
+
+#include <device/pci_def.h>
+
+#define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
+
+#if !defined(__SIMPLE_DEVICE__)
+#include <device/device.h>
+#define _PCH_DEV(slot, func)	pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
+#else
+#define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
+#endif
+
+/* System Agent Devices */
+
+#define SA_DEV_SLOT_ROOT	0x00
+#define  SA_DEVFN_ROOT		PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
+#if defined(__SIMPLE_DEVICE__)
+#define  SA_DEV_ROOT		PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
+#endif
+
+#define SA_DEV_SLOT_IGD		0x02
+#define  SA_DEVFN_IGD		PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
+#define  SA_DEV_IGD		PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
+
+#define SA_DEV_SLOT_DPTF	0x04
+#define  SA_DEVFN_DPTF		PCI_DEVFN(SA_DEV_SLOT_DPTF, 0)
+#define  SA_DEV_DPTF		PCI_DEV(0, SA_DEV_SLOT_DPTF, 0)
+
+#define SA_DEV_SLOT_CPU_PCIE	0x06
+#define  SA_DEVFN_CPU_PCIE	PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0)
+
+#define SA_DEV_SLOT_TBT		0x07
+#define SA_DEVFN_TBT(x)		PCI_DEVFN(SA_DEV_SLOT_TBT, (x))
+#define NUM_TBT_FUNCTIONS	4
+#define  SA_DEVFN_TBT0		PCI_DEVFN(SA_DEV_SLOT_TBT, 0)
+#define  SA_DEVFN_TBT1		PCI_DEVFN(SA_DEV_SLOT_TBT, 1)
+#define  SA_DEVFN_TBT2		PCI_DEVFN(SA_DEV_SLOT_TBT, 2)
+#define  SA_DEVFN_TBT3		PCI_DEVFN(SA_DEV_SLOT_TBT, 3)
+#define  SA_DEV_TBT0		PCI_DEV(0, SA_DEV_SLOT_TBT, 0)
+#define  SA_DEV_TBT1		PCI_DEV(0, SA_DEV_SLOT_TBT, 1)
+#define  SA_DEV_TBT2		PCI_DEV(0, SA_DEV_SLOT_TBT, 2)
+#define  SA_DEV_TBT3		PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
+
+#define SA_DEV_SLOT_TCSS	0x0d
+#define  SA_DEVFN_TCSS_XHCI	PCI_DEVFN(SA_DEV_SLOT_TCSS, 0)
+#define  SA_DEVFN_TCSS_XDCI	PCI_DEVFN(SA_DEV_SLOT_TCSS, 1)
+#define  SA_DEVFN_TCSS_DMA0	PCI_DEVFN(SA_DEV_SLOT_TCSS, 2)
+#define  SA_DEVFN_TCSS_DMA1	PCI_DEVFN(SA_DEV_SLOT_TCSS, 3)
+#define  SA_DEV_TCSS_XHCI	PCI_DEV(0, SA_DEV_SLOT_TCSS, 0)
+#define  SA_DEV_TCSS_XDCI	PCI_DEV(0, SA_DEV_SLOT_TCSS, 1)
+#define  SA_DEV_TCSS_DMA0	PCI_DEV(0, SA_DEV_SLOT_TCSS, 2)
+#define  SA_DEV_TCSS_DMA1	PCI_DEV(0, SA_DEV_SLOT_TCSS, 3)
+
+#define SA_DEV_SLOT_VMD		0x0e
+#define  SA_DEVFN_VMD		PCI_DEVFN(SA_DEV_SLOT_VMD, 0)
+#define  SA_DEV_VMD		PCI_DEV(0, SA_DEV_SLOT_VMD, 0)
+
+/* PCH Devices */
+#define PCH_DEV_SLOT_SIO0	0x10
+#define  PCH_DEVFN_THC0		_PCH_DEVFN(SIO0, 0)
+#define  PCH_DEVFN_THC1		_PCH_DEVFN(SIO0, 1)
+#define  PCH_DEV_THC0		_PCH_DEV(SIO0, 0)
+#define  PCH_DEV_THC1		_PCH_DEV(SIO0, 1)
+
+#define PCH_DEV_SLOT_ISH	0x12
+#define  PCH_DEVFN_ISH		_PCH_DEVFN(ISH, 0)
+#define  PCH_DEVFN_GSPI2	_PCH_DEVFN(ISH, 6)
+#define  PCH_DEV_ISH		_PCH_DEV(ISH, 0)
+#define  PCH_DEV_GSPI2		_PCH_DEV(ISH, 6)
+
+#define PCH_DEV_SLOT_XHCI	0x14
+#define  PCH_DEVFN_XHCI		_PCH_DEVFN(XHCI, 0)
+#define  PCH_DEVFN_USBOTG	_PCH_DEVFN(XHCI, 1)
+#define  PCH_DEVFN_SRAM		_PCH_DEVFN(XHCI, 2)
+#define  PCH_DEVFN_CNVI_WIFI	_PCH_DEVFN(XHCI, 3)
+#define  PCH_DEV_XHCI		_PCH_DEV(XHCI, 0)
+#define  PCH_DEV_USBOTG		_PCH_DEV(XHCI, 1)
+#define  PCH_DEV_SRAM		_PCH_DEV(XHCI, 2)
+#define  PCH_DEV_CNVI_WIFI	_PCH_DEV(XHCI, 3)
+
+#define PCH_DEV_SLOT_SIO3	0x15
+#define  PCH_DEVFN_I2C0		_PCH_DEVFN(SIO3, 0)
+#define  PCH_DEVFN_I2C1		_PCH_DEVFN(SIO3, 1)
+#define  PCH_DEVFN_I2C2		_PCH_DEVFN(SIO3, 2)
+#define  PCH_DEVFN_I2C3		_PCH_DEVFN(SIO3, 3)
+#define  PCH_DEV_I2C0		_PCH_DEV(SIO3, 0)
+#define  PCH_DEV_I2C1		_PCH_DEV(SIO3, 1)
+#define  PCH_DEV_I2C2		_PCH_DEV(SIO3, 2)
+#define  PCH_DEV_I2C3		_PCH_DEV(SIO3, 3)
+
+#define PCH_DEV_SLOT_CSE	0x16
+#define  PCH_DEVFN_CSE		_PCH_DEVFN(CSE, 0)
+#define  PCH_DEVFN_CSE_2	_PCH_DEVFN(CSE, 1)
+#define  PCH_DEVFN_CSE_IDER	_PCH_DEVFN(CSE, 2)
+#define  PCH_DEVFN_CSE_KT	_PCH_DEVFN(CSE, 3)
+#define  PCH_DEVFN_CSE_3	_PCH_DEVFN(CSE, 4)
+#define  PCH_DEVFN_CSE_4	_PCH_DEVFN(CSE, 5)
+#define  PCH_DEV_CSE		_PCH_DEV(CSE, 0)
+#define  PCH_DEV_CSE_2		_PCH_DEV(CSE, 1)
+#define  PCH_DEV_CSE_IDER	_PCH_DEV(CSE, 2)
+#define  PCH_DEV_CSE_KT		_PCH_DEV(CSE, 3)
+#define  PCH_DEV_CSE_3		_PCH_DEV(CSE, 4)
+#define  PCH_DEV_CSE_4		_PCH_DEV(CSE, 5)
+
+#define PCH_DEV_SLOT_SATA	0x17
+#define  PCH_DEVFN_SATA		_PCH_DEVFN(SATA, 0)
+#define  PCH_DEV_SATA		_PCH_DEV(SATA, 0)
+
+#define PCH_DEV_SLOT_SIO4	0x19
+#define  PCH_DEVFN_I2C4		_PCH_DEVFN(SIO4, 0)
+#define  PCH_DEVFN_I2C5		_PCH_DEVFN(SIO4, 1)
+#define  PCH_DEVFN_UART2	_PCH_DEVFN(SIO4, 2)
+#define  PCH_DEV_I2C4		_PCH_DEV(SIO4, 0)
+#define  PCH_DEV_I2C5		_PCH_DEV(SIO4, 1)
+#define  PCH_DEV_UART2		_PCH_DEV(SIO4, 2)
+
+#define PCH_DEV_SLOT_PCIE	0x1c
+#define  PCH_DEVFN_PCIE1	_PCH_DEVFN(PCIE, 0)
+#define  PCH_DEVFN_PCIE2	_PCH_DEVFN(PCIE, 1)
+#define  PCH_DEVFN_PCIE3	_PCH_DEVFN(PCIE, 2)
+#define  PCH_DEVFN_PCIE4	_PCH_DEVFN(PCIE, 3)
+#define  PCH_DEVFN_PCIE5	_PCH_DEVFN(PCIE, 4)
+#define  PCH_DEVFN_PCIE6	_PCH_DEVFN(PCIE, 5)
+#define  PCH_DEVFN_PCIE7	_PCH_DEVFN(PCIE, 6)
+#define  PCH_DEVFN_PCIE8	_PCH_DEVFN(PCIE, 7)
+#define  PCH_DEV_PCIE1		_PCH_DEV(PCIE, 0)
+#define  PCH_DEV_PCIE2		_PCH_DEV(PCIE, 1)
+#define  PCH_DEV_PCIE3		_PCH_DEV(PCIE, 2)
+#define  PCH_DEV_PCIE4		_PCH_DEV(PCIE, 3)
+#define  PCH_DEV_PCIE5		_PCH_DEV(PCIE, 4)
+#define  PCH_DEV_PCIE6		_PCH_DEV(PCIE, 5)
+#define  PCH_DEV_PCIE7		_PCH_DEV(PCIE, 6)
+#define  PCH_DEV_PCIE8		_PCH_DEV(PCIE, 7)
+
+#define PCH_DEV_SLOT_PCIE_1	0x1d
+#define  PCH_DEVFN_PCIE9	_PCH_DEVFN(PCIE_1, 0)
+#define  PCH_DEVFN_PCIE10	_PCH_DEVFN(PCIE_1, 1)
+#define  PCH_DEVFN_PCIE11	_PCH_DEVFN(PCIE_1, 2)
+#define  PCH_DEVFN_PCIE12	_PCH_DEVFN(PCIE_1, 3)
+#define  PCH_DEV_PCIE9		_PCH_DEV(PCIE_1, 0)
+#define  PCH_DEV_PCIE10		_PCH_DEV(PCIE_1, 1)
+#define  PCH_DEV_PCIE11		_PCH_DEV(PCIE_1, 2)
+#define  PCH_DEV_PCIE12		_PCH_DEV(PCIE_1, 3)
+
+#define PCH_DEV_SLOT_SIO5	0x1e
+#define  PCH_DEVFN_UART0	_PCH_DEVFN(SIO5, 0)
+#define  PCH_DEVFN_UART1	_PCH_DEVFN(SIO5, 1)
+#define  PCH_DEVFN_GSPI0	_PCH_DEVFN(SIO5, 2)
+#define  PCH_DEVFN_GSPI1	_PCH_DEVFN(SIO5, 3)
+#define  PCH_DEV_UART0		_PCH_DEV(SIO5, 0)
+#define  PCH_DEV_UART1		_PCH_DEV(SIO5, 1)
+#define  PCH_DEV_GSPI0		_PCH_DEV(SIO5, 2)
+#define  PCH_DEV_GSPI1		_PCH_DEV(SIO5, 3)
+
+#define PCH_DEV_SLOT_ESPI	0x1f
+#define PCH_DEV_SLOT_LPC	PCH_DEV_SLOT_ESPI
+#define  PCH_DEVFN_ESPI		_PCH_DEVFN(ESPI, 0)
+#define  PCH_DEVFN_P2SB		_PCH_DEVFN(ESPI, 1)
+#define  PCH_DEVFN_PMC		_PCH_DEVFN(ESPI, 2)
+#define  PCH_DEVFN_HDA		_PCH_DEVFN(ESPI, 3)
+#define  PCH_DEVFN_SMBUS	_PCH_DEVFN(ESPI, 4)
+#define  PCH_DEVFN_SPI		_PCH_DEVFN(ESPI, 5)
+#define  PCH_DEVFN_GBE		_PCH_DEVFN(ESPI, 6)
+#define  PCH_DEVFN_TRACEHUB	_PCH_DEVFN(ESPI, 7)
+#define  PCH_DEV_ESPI		_PCH_DEV(ESPI, 0)
+#define  PCH_DEV_LPC		PCH_DEV_ESPI
+#define  PCH_DEV_P2SB		_PCH_DEV(ESPI, 1)
+
+#if !ENV_RAMSTAGE
+/*
+ * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets
+ * hidden from PCI bus after call to FSP-S. This leads to resource allocator
+ * dropping it from the root bus as unused device. All references to PCH_DEV_PMC
+ * would then return NULL and can go unnoticed if not handled properly. Since,
+ * this device does not have any special chip config associated with it, it is
+ * okay to not provide the definition for it in ramstage.
+ */
+#define  PCH_DEV_PMC		_PCH_DEV(ESPI, 2)
+#endif
+
+#define  PCH_DEV_HDA		_PCH_DEV(ESPI, 3)
+#define  PCH_DEV_SMBUS		_PCH_DEV(ESPI, 4)
+#define  PCH_DEV_SPI		_PCH_DEV(ESPI, 5)
+#define  PCH_DEV_GBE		_PCH_DEV(ESPI, 6)
+#define  PCH_DEV_TRACEHUB	_PCH_DEV(ESPI, 7)
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h
new file mode 100644
index 0000000000..baeb7083d7
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Alder Lake Processor PCH Datasheet
+ * Document number: 621483
+ * Chapter number: 31-35
+ */
+
+#ifndef SOC_ALDERLAKE_PCR_H
+#define SOC_ALDERLAKE_PCR_H
+
+/*
+ * Port ids
+ */
+#define PID_GPIOCOM0	0x6e
+#define PID_GPIOCOM1	0x6d
+#define PID_GPIOCOM2	0x6c
+#define PID_GPIOCOM3	0x6b
+#define PID_GPIOCOM4	0x6a
+#define PID_GPIOCOM5	0x69
+
+#define PID_ESPI	0x72
+#define PID_DMI		0x88
+#define PID_PSTH	0x89
+#define PID_CSME0	0x90
+#define PID_ISCLK	0xad
+#define PID_PSF1	0xba
+#define PID_PSF2	0xbb
+#define PID_PSF3	0xbc
+#define PID_PSF4	0xbd
+#define PID_RTC		0xc3
+#define PID_ITSS	0xc4
+#define PID_SERIALIO	0xcb
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/pm.h b/src/soc/intel/alderlake/include/soc/pm.h
new file mode 100644
index 0000000000..b65b24dc46
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/pm.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Alder Lake Processor PCH Datasheet
+ * Document number: 621483
+ * Chapter number: 4
+ */
+
+#ifndef _SOC_PM_H_
+#define _SOC_PM_H_
+
+#define PM1_STS			0x00
+#define  WAK_STS		(1 << 15)
+#define  PCIEXPWAK_STS		(1 << 14)
+#define  PRBTNOR_STS		(1 << 11)
+#define  RTC_STS		(1 << 10)
+#define  PWRBTN_STS		(1 << 8)
+#define  GBL_STS		(1 << 5)
+#define  BM_STS			(1 << 4)
+#define  TMROF_STS		(1 << 0)
+#define PM1_EN			0x02
+#define  PCIEXPWAK_DIS		(1 << 14)
+#define  RTC_EN			(1 << 10)
+#define  PWRBTN_EN		(1 << 8)
+#define  GBL_EN			(1 << 5)
+#define  TMROF_EN		(1 << 0)
+#define PM1_CNT			0x04
+#define  GBL_RLS		(1 << 2)
+#define  BM_RLD			(1 << 1)
+#define  SCI_EN			(1 << 0)
+#define PM1_TMR			0x08
+#define SMI_EN			0x30
+#define  XHCI_SMI_EN		(1 << 31)
+#define  ME_SMI_EN		(1 << 30)
+#define  ESPI_SMI_EN		(1 << 28)
+#define  GPIO_UNLOCK_SMI_EN	(1 << 27)
+#define  INTEL_USB2_EN		(1 << 18)
+#define  LEGACY_USB2_EN		(1 << 17)
+#define  PERIODIC_EN		(1 << 14)
+#define  TCO_SMI_EN		(1 << 13)
+#define  MCSMI_EN		(1 << 11)
+#define  BIOS_RLS		(1 <<  7)
+#define  SWSMI_TMR_EN		(1 <<  6)
+#define  APMC_EN		(1 <<  5)
+#define  SLP_SMI_EN		(1 <<  4)
+#define  LEGACY_USB_EN		(1 <<  3)
+#define  BIOS_EN		(1 <<  2)
+#define  EOS			(1 <<  1)
+#define  GBL_SMI_EN		(1 <<  0)
+#define SMI_STS			0x34
+#define  SMI_STS_BITS			32
+#define  XHCI_SMI_STS_BIT		31
+#define  ME_SMI_STS_BIT			30
+#define  ESPI_SMI_STS_BIT		28
+#define  GPIO_UNLOCK_SMI_STS_BIT	27
+#define  SPI_SMI_STS_BIT		26
+#define  SCC_SMI_STS_BIT		25
+#define  MONITOR_STS_BIT		21
+#define  PCI_EXP_SMI_STS_BIT		20
+#define  SMBUS_SMI_STS_BIT		16
+#define  SERIRQ_SMI_STS_BIT		15
+#define  PERIODIC_STS_BIT		14
+#define  TCO_STS_BIT			13
+#define  DEVMON_STS_BIT			12
+#define  MCSMI_STS_BIT			11
+#define  GPIO_STS_BIT			10
+#define  GPE0_STS_BIT			9
+#define  PM1_STS_BIT			8
+#define  SWSMI_TMR_STS_BIT		6
+#define  APM_STS_BIT			5
+#define  SMI_ON_SLP_EN_STS_BIT		4
+#define  LEGACY_USB_STS_BIT		3
+#define  BIOS_STS_BIT			2
+#define GPE_CNTL		0x42
+#define  SWGPE_CTRL		(1 << 1)
+#define DEVACT_STS		0x44
+#define PM2_CNT			0x50
+
+#define GPE0_REG_MAX		4
+#define GPE0_REG_SIZE		32
+#define GPE0_STS(x)		(0x60 + ((x) * 4))
+#define  GPE_31_0		0	/* 0x60/0x70 = GPE[31:0] */
+#define  GPE_63_32		1	/* 0x64/0x74 = GPE[63:32] */
+#define  GPE_95_64		2	/* 0x68/0x78 = GPE[95:64] */
+#define  GPE_STD		3	/* 0x6c/0x7c = Standard GPE */
+#define GPE_STS_RSVD            GPE_STD
+#define   WADT_STS		(1 << 18)
+#define   GPIO_T2_STS		(1 << 15)
+#define   ESPI_STS		(1 << 14)
+#define   PME_B0_STS		(1 << 13)
+#define   ME_SCI_STS		(1 << 12)
+#define   PME_STS		(1 << 11)
+#define   BATLOW_STS		(1 << 10)
+#define   PCI_EXP_STS		(1 << 9)
+#define   SMB_WAK_STS		(1 << 7)
+#define   TCOSCI_STS		(1 << 6)
+#define   SWGPE_STS		(1 << 2)
+#define   HOT_PLUG_STS		(1 << 1)
+#define GPE0_EN(x)		(0x70 + ((x) * 4))
+#define   WADT_EN		(1 << 18)
+#define   GPIO_T2_EN		(1 << 15)
+#define   ESPI_EN		(1 << 14)
+#define   PME_B0_EN_BIT		13
+#define   PME_B0_EN		(1 << PME_B0_EN_BIT)
+#define   ME_SCI_EN		(1 << 12)
+#define   PME_EN		(1 << 11)
+#define   BATLOW_EN		(1 << 10)
+#define   PCI_EXP_EN		(1 << 9)
+#define   TCOSCI_EN		(1 << 6)
+#define   SWGPE_EN		(1 << 2)
+#define   HOT_PLUG_EN		(1 << 1)
+
+#define EN_BLOCK		3
+
+/*
+ * Enable SMI generation:
+ *  - on APMC writes (io 0xb2)
+ *  - on writes to SLP_EN (sleep states)
+ *  - on writes to GBL_RLS (bios commands)
+ *  - on eSPI events (does nothing on LPC systems)
+ * No SMIs:
+ *  - on TCO events, unless enabled in common code
+ *  - on microcontroller writes (io 0x62/0x66)
+ */
+#define ENABLE_SMI_PARAMS \
+	(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
+
+#define	PSS_RATIO_STEP		2
+#define	PSS_MAX_ENTRIES		8
+#define	PSS_LATENCY_TRANSITION	10
+#define	PSS_LATENCY_BUSMASTER	10
+
+#if !defined(__ACPI__)
+
+#include <acpi/acpi.h>
+#include <soc/gpe.h>
+#include <soc/iomap.h>
+#include <soc/smbus.h>
+#include <soc/pmc.h>
+
+struct chipset_power_state {
+	uint16_t pm1_sts;
+	uint16_t pm1_en;
+	uint32_t pm1_cnt;
+	uint16_t tco1_sts;
+	uint16_t tco2_sts;
+	uint32_t gpe0_sts[4];
+	uint32_t gpe0_en[4];
+	uint32_t gen_pmcon_a;
+	uint32_t gen_pmcon_b;
+	uint32_t gblrst_cause[2];
+	uint32_t hpr_cause0;
+	uint32_t prev_sleep_state;
+} __packed;
+
+/* Get base address PMC memory mapped registers. */
+uint8_t *pmc_mmio_regs(void);
+
+/* Get base address of TCO I/O registers. */
+uint16_t smbus_tco_regs(void);
+
+/* Set the DISB after DRAM init */
+void pmc_set_disb(void);
+
+/* Clear PMCON status bits */
+void pmc_clear_pmcon_sts(void);
+
+/* STM Support */
+uint16_t get_pmbase(void);
+#endif /* !defined(__ACPI__) */
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/smbus.h b/src/soc/intel/alderlake/include/soc/smbus.h
new file mode 100644
index 0000000000..ab4994aa37
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/smbus.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Alder Lake Processor PCH Datasheet
+ * Document number: 621483
+ * Chapter number: 6
+ */
+
+#ifndef _SOC_ALDERLAKE_SMBUS_H_
+#define _SOC_ALDERLAKE_SMBUS_H_
+
+/* IO and MMIO registers under primary BAR */
+
+/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
+#define TCO1_STS			0x04
+#define  TCO_TIMEOUT			(1 << 3)
+#define TCO2_STS			0x06
+#define  TCO_STS_SECOND_TO		(1 << 1)
+#define  TCO_INTRD_DET			(1 << 0)
+#define TCO1_CNT			0x08
+#define  TCO_LOCK			(1 << 12)
+#define  TCO_TMR_HLT			(1 << 11)
+#define TCO2_CNT			0x0A
+#define  TCO_INTRD_SEL_MASK		(3 << 1)
+#define  TCO_INTRD_SEL_SMI		(1 << 2)
+#define  TCO_INTRD_SEL_INT		(1 << 1)
+
+/*
+ * Default slave address value for PCH. This value is set to match default
+ * value set by hardware. It is useful since PCH is able to respond even
+ * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
+ */
+#define SMBUS_SLAVE_ADDR		0x44
+
+#endif