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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-08-07 12:16:09 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-08-08 01:51:45 +0000 |
| commit | c7b23e9dc8d2efca8476c46b4879e4958b420f36 (patch) | |
| tree | 4e8e943f025fe4520ab8d8f530fa7ff0d16b21b3 /src/soc/intel | |
| parent | 94e2ec72531c9a0d99081381f3ce3a82a6754af3 (diff) | |
| download | coreboot-c7b23e9dc8d2efca8476c46b4879e4958b420f36.tar.xz | |
src/soc/intel/common: Configure the gspi chip select state correctly
This implementation updates the chip select control register
programming in gspi controller setup call to program the correct
bit fields for chip select state.
Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/27889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/gspi/gspi.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 35c34cecbc..fc7dd46ad8 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -481,12 +481,9 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) cs_ctrl = CS_MODE_SW | CS_0; pol = gspi_csctrl_polarity(cfg.cs_polarity); cs_ctrl |= pol << CS_0_POL_SHIFT; - cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT); + cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT) << CS_STATE_SHIFT; gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl); - /* De-assert chip select. */ - __gspi_cs_change(p, CS_DEASSERT); - /* Disable SPI controller. */ gspi_write_mmio_reg(p, SSCR0, SSCR0_SSE_DISABLE); |