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authorGaggery Tsai <gaggery.tsai@intel.com>2019-02-18 20:32:11 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-02-21 11:29:46 +0000
commitd01a995cd3e1adfd5af28a980eedac1fee0dddc1 (patch)
tree8efaba2a815f9ed2ffce8a2379fe59e68128187e /src/soc/intel
parent5620b105461cc18cf1439f02013153237f372b4b (diff)
downloadcoreboot-d01a995cd3e1adfd5af28a980eedac1fee0dddc1.tar.xz
src/soc/intel/cannonlake: Add PsysPmax setting
This patch feeds PsysPmax setting to FSP through UPD and adds a psys_pmax member in chip information so that we can set PsysPmax through DT. The PsysPmax needs to be set correctly mapping to maximum system power. Otherwise, system performance would be limited due to the default PsysPmax setting in FSP is only 21W. BUG=None BRANCH=None TEST=Set psys_pmax to an example value eg 101 in DT && put debug code in FSP to print the PsysPmax value before sending to Pcode, ensure the setting is correctly programmed. Change-Id: Ia88ea17bc661a388c5b9bc3e59abc27c9f262977 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/31505 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/chip.h2
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c7
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index cb9ad3827f..1f26f1e146 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -216,6 +216,8 @@ struct soc_intel_cannonlake_config {
uint32_t tdp_psyspl3_dutycycle;
/* PL4 Value in Watts */
uint32_t tdp_pl4;
+ /* Estimated maximum platform power in Watts */
+ uint16_t psys_pmax;
/* Intel Speed Shift Technology */
uint8_t speed_shift_enable;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index c276c862e8..a198f1bfec 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -88,6 +88,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
mainboard_silicon_init_params(params);
+ /* Set PsysPmax if it is available from DT */
+ if (config->psys_pmax) {
+ printk(BIOS_DEBUG, "psys_pmax = %dW\n", config->psys_pmax);
+ /* PsysPmax is in unit of 1/8 Watt */
+ tconfig->PsysPmax = config->psys_pmax * 8;
+ }
+
/* Unlock upper 8 bytes of RTC RAM */
params->PchLockDownRtcMemoryLock = 0;