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authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-07-10 18:33:28 +0300
committerMartin Roth <martinroth@google.com>2019-07-21 18:53:00 +0000
commitf357f7e264baf35f98e216ac59abe71770147f40 (patch)
tree9b8c09a5282ed0d0fc78e2e3df695d1a97757e58 /src/soc/intel
parent6f76d0b12fcc04a118cb8827b58f56f395435fbb (diff)
downloadcoreboot-f357f7e264baf35f98e216ac59abe71770147f40.tar.xz
soc/intel/common: add PAD_CFG_NF_BUF_TRIG macro
In the case there is no the circuit diagram for motherboard, the PCH/SoC GPIOs config is based on information from the inteltool dump. However, available macros from gpio_defs.h can't define the pad configuration from this dump: 0x0440: 0x0000002084000500 GPP_A8 CLKRUN# 0x0448: 0x0000102184000600 GPP_A9 CLKOUT_LPC0 0x0450: 0x0000102284000600 GPP_A10 CLKOUT_LPC1 To convert these raw DW0/DW1 register values to macros, the following parameters must be set: func - pad function, pull - termination, rst - pad reset config, trig - rx level/edge configuration, bufdis - rx/tx (in/output) buffer disable. The patch resolves the above problem by adding a new macro for the native function configuration: PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) These changes were tested on Asrock H110M-DVS motherboard [2]. It also resolves the problem of automatically creating pads configuration [3,4] [1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/33565 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1 [4] https://github.com/maxpoliak/pch-pads-parser/commit/215d303 Change-Id: If9fe50ff9a680633db6228564345200c0e1ee3ea Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34337 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/gpio_defs.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index e1ddd4babb..0a3e11737a 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -134,6 +134,15 @@
#define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value
#define PAD_PULL(value) PAD_CFG1_PULL_##value
+/* Disable the input/output buffer of the pad */
+#define PAD_CFG0_BUF_NO_DISABLE (0)
+#define PAD_CFG0_BUF_TX_DISABLE PAD_CFG0_TX_DISABLE
+#define PAD_CFG0_BUF_RX_DISABLE PAD_CFG0_RX_DISABLE
+#define PAD_CFG0_BUF_TX_RX_DISABLE \
+ (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE)
+
+#define PAD_BUF(value) PAD_CFG0_BUF_##value
+
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value
#define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value
@@ -180,6 +189,15 @@
_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
PAD_IOSSTATE(TxLASTRxE))
+/*
+ * Set native function with RX Level/Edge configuration and disable
+ * input/output buffer if necessary
+ */
+#define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \
+ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_CFG0_TRIG_##trig | \
+ PAD_BUF(bufdis) | PAD_FUNC(func), \
+ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
+
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
/* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S
Not applicable to all SOCs. Refer EDS