diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-09 12:09:43 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-10 05:26:46 +0000 |
| commit | fed1a1a8b00273d707b8512d59f12f0b48fbc7c9 (patch) | |
| tree | 4424dd264aa7554b094e0d81c2dd988b6dde1b3a /src/soc/intel | |
| parent | 4df75dc49834a0d93321d6ec28e39da6fb5542fd (diff) | |
| download | coreboot-fed1a1a8b00273d707b8512d59f12f0b48fbc7c9.tar.xz | |
soc/intel/alderlake: Rename pch_init() code
Rename the pch_init function to bootblock_pch_init to
maintain the parity with previous generation SoC code block.
Refer to commit 1201696.
Change-Id: Id2a89b2f64b58079062d79e07efbdcfad7ed3d2d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45189
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/bootblock.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/pch.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/bootblock.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c index e7d97c50bf..96e6268f74 100644 --- a/src/soc/intel/alderlake/bootblock/bootblock.c +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -25,7 +25,7 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { report_platform_info(); - pch_init(); + bootblock_pch_init(); /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 8452d83290..b7d2c15d3c 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -138,7 +138,7 @@ void pch_early_iorange_init(void) pch_enable_lpc(); } -void pch_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h index 9816b317db..087d29f741 100644 --- a/src/soc/intel/alderlake/include/soc/bootblock.h +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -8,7 +8,7 @@ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ -void pch_init(void); +void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); |