diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-05-16 21:41:35 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-20 00:35:10 +0000 |
| commit | 01750ef8d725895f984c0ae373bab83a925130f0 (patch) | |
| tree | ad69cab0fcf266d25ea5297966f5057e723d84fc /src/soc/intel | |
| parent | c336130c4467a94929c71a9cff1c28c2159ef21b (diff) | |
| download | coreboot-01750ef8d725895f984c0ae373bab83a925130f0.tar.xz | |
soc/intel/skylake: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: I2ff7a30fabb7f77d13acadec1e6e4cb3a45b6139
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/acpi/systemagent.asl | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index b2e691ddf8..962d9ef879 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -187,14 +187,20 @@ Method (_CRS, 0, Serialized) /* * Fix up PCI memory region * Start with Top of Lower Usable DRAM + * Lower 20 bits of TOLUD register need to be masked since they contain lock and + * reserved bits. */ - Local0 = \_SB.PCI0.MCHC.TLUD + Local0 = \_SB.PCI0.MCHC.TLUD & (0xfff << 20) Local1 = \_SB.PCI0.MCHC.MEBA /* Check if ME base is equal */ If (Local0 == Local1) { - /* Use Top Of Memory instead */ - Local0 = \_SB.PCI0.MCHC.TOM + /* + * Use Top Of Memory instead + * Lower 20 bits of TOM register need to be masked since they contain lock and + * reserved bits. + */ + Local0 = \_SB.PCI0.MCHC.TOM & (0x7ffff << 20) } Store (Local0, PMIN) |