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authorJohnny Lin <johnny_lin@wiwynn.com>2020-08-04 18:01:54 +0800
committerAngel Pons <th3fanbus@gmail.com>2020-08-07 12:37:04 +0000
commit12bee2af237afb6736a91d3f526789efb0542aeb (patch)
treecdbb171d08ad8eb95de319498565a6f5800acac0 /src/soc/intel
parent159d0f0ed7302b214e2e43c5c6041f3d598aab66 (diff)
downloadcoreboot-12bee2af237afb6736a91d3f526789efb0542aeb.tar.xz
xeon_sp/cpx: Enable HWP Intel Speed Shift
Set HWP base feature, enable EPP, lock thermal interrupt and lock MSR Tested=On OCP Delta Lake, rdmsr 0x1aa shows 403040 Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44171 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/xeon_sp/cpx/cpu.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 1df5c1350c..cf903b872a 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -64,6 +64,18 @@ static void each_cpu_init(struct device *cpu)
__func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id);
setup_lapic();
+ /*
+ * Set HWP base feature, EPP reg enumeration, lock thermal and msr
+ * This is package level MSR. Need to check if it updates correctly on
+ * multi-socket platform.
+ */
+ msr = rdmsr(MSR_MISC_PWR_MGMT);
+ if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */
+ msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR |
+ LOCK_THERM_INT);
+ wrmsr(MSR_MISC_PWR_MGMT, msr);
+ }
+
/* Enable Fast Strings */
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= FAST_STRINGS_ENABLE_BIT;