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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-09-01 16:10:06 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-09-08 05:25:14 +0000
commit4cba419676de40c76e4979957baf6039da8b8bf5 (patch)
tree84b609f95f50e1022005022fa4639b501e8a1fe7 /src/soc/intel
parent62669a24eaf5236a60eebf8e26eefc984ca321ee (diff)
downloadcoreboot-4cba419676de40c76e4979957baf6039da8b8bf5.tar.xz
soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP
The IA32_MTRR_CAP register has a bit which indicates that the SMRR MSRs can be "locked" and this patch adds the definition for that. BUG=b:164489598 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1254fb40c790f2a83dd11c2aabcf9bdf922b9395 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/msr.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 82874f9224..4aa069e068 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -106,8 +106,9 @@
#define MSR_L2_QOS_MASK(reg) (0xd10 + reg)
/* MTRR_CAP_MSR bits */
-#define SMRR_SUPPORTED (1<<11)
-#define PRMRR_SUPPORTED (1<<12)
+#define SMRR_SUPPORTED (1<<11)
+#define PRMRR_SUPPORTED (1<<12)
+#define SMRR_LOCK_SUPPORTED (1<<14)
#define SGX_SUPPORTED (1<<2)
/* Intel SDM: Table 36-6.