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| author | Huayang Duan <huayang.duan@mediatek.com> | 2018-10-23 16:05:24 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-26 11:20:35 +0000 |
| commit | bb7f4c7a4f3a076ba3e52fea9228e4a064316128 (patch) | |
| tree | 42e496c03922bcd91d01b5772d1d0f660088d4ce /src/soc/intel | |
| parent | 0f5d7b9daf3b2c7a2991c62580c9db9c3e8ac953 (diff) | |
| download | coreboot-bb7f4c7a4f3a076ba3e52fea9228e4a064316128.tar.xz | |
mediatek/mt8183: Correct MPU ctrl register address
Remove unused members in emi_mpu_regs and sdram_params. Change
mpu_ctrl_d to array so the offset (0x804) for D1 is corrected.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: I95c002058dc5e1cba868334fecf8f42bd3e497e6
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/29251
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions