diff options
| author | Patrick Georgi <pgeorgi@google.com> | 2017-10-05 18:19:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-10-06 17:07:23 +0000 |
| commit | c6a005019874fed9a9f663953a850b76a5fbf96c (patch) | |
| tree | ed34805925a4f3237d4283f7646377766b562822 /src/soc/intel | |
| parent | 9d3de2649f46cc85269b4877f0d6e715a4fec5aa (diff) | |
| download | coreboot-c6a005019874fed9a9f663953a850b76a5fbf96c.tar.xz | |
soc/intel/skylake: use locate_vbt directly instead of calling a wrapper
Change-Id: I65c423660ab1778f5dd9243e428a4d005bd1699a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index ac60125f70..f9bdf8a1ef 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -28,6 +28,7 @@ #include <fsp/util.h> #include <romstage_handoff.h> #include <soc/acpi.h> +#include <soc/intel/common/vbt.h> #include <soc/interrupt.h> #include <soc/irq.h> #include <soc/pci_devs.h> @@ -116,9 +117,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Load VBT */ if (is_s3_wakeup) { printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n"); - } else if (display_init_required()) { + } else if (display_init_required() && IS_ENABLED(CONFIG_RUN_FSP_GOP)) { /* Get VBT data */ - vbt_data = fsp_load_vbt(); + vbt_data = (uintptr_t)locate_vbt(); if (vbt_data) printk(BIOS_DEBUG, "Passing VBT to GOP\n"); else |