summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorLee Leahy <leroy.p.leahy@intel.com>2016-08-05 06:11:19 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2016-08-05 15:36:18 +0200
commitd924fac75942db4362af5dd026ef2b0768ffb5ce (patch)
treec8f07cd105c1851b76aa31ed27103a4f2c31de81 /src/soc/intel
parentbcbb205454854c878c80c4aca16a04dc46af090a (diff)
downloadcoreboot-d924fac75942db4362af5dd026ef2b0768ffb5ce.tar.xz
soc/intel/quark: Add missing breaks
Add missing breaks in reg_access.c. TEST=Build and run on Galileo Gen2 Found-by: Converity Scan #1361261 Change-Id: I8be57f0758e5918a605e20ab9002747e0cc958e0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16069 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/quark/reg_access.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c
index 3d530b9982..2ddb99b460 100644
--- a/src/soc/intel/quark/reg_access.c
+++ b/src/soc/intel/quark/reg_access.c
@@ -163,9 +163,11 @@ static void reg_cpu_cr_write(uint32_t reg_address, CRx_TYPE value)
case 0:
write_cr0(value);
+ break;
case 4:
write_cr4(value);
+ break;
}
}