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authorJeremy Soller <jeremy@system76.com>2019-10-09 12:14:48 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-10-21 09:08:03 +0000
commite2fafc0c8cd45c9365a1aa5b1276a6ab46b6a143 (patch)
tree65e086763e5dcd61d5d526a47c1813b2c7157208 /src/soc/intel
parent7783c606a4694c39d2da26d10cf6b3ad036dfa81 (diff)
downloadcoreboot-e2fafc0c8cd45c9365a1aa5b1276a6ab46b6a143.tar.xz
Revert "soc/intel/cannonlake: Remove DMA support for PTT"
This reverts commit d5018a8f78b9e1f0b7d3d1be298cba9716b10c6c. Reason for revert: Breaks boot on Whiskey Lake-U boards Both System76 and Purism have had memory initialization failures when this patch is applied, with the following error message: Failed to accommodate FSP reserved memory request! An extra 4096 bytes needs to be reserved for the FSP on these systems, and reinstating the PTT reservation does this as expected. PTT is enabled for the System76 galp3-c in the ME configuration, which is why the behaviour is different. Signed-off-by: Jeremy Soller <jeremy@system76.com> CC: Matt DeVillier <matt.devillier@gmail.com> CC: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib82f02c4a2b1cd2dbf95d4ca4a9edd314e78edd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35924 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/include/soc/iomap.h4
-rw-r--r--src/soc/intel/cannonlake/memmap.c19
2 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index 1ebaf3f7b6..9cfb59e7d0 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -68,6 +68,10 @@
#define HECI1_BASE_ADDRESS 0xfeda2000
+/* PTT registers */
+#define PTT_TXT_BASE_ADDRESS 0xfed30800
+#define PTT_PRESENT 0x00070000
+
#define VTD_BASE_ADDRESS 0xFED90000
#define VTD_BASE_SIZE 0x00004000
/*
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index f3286cce66..7adaa30b18 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -37,6 +37,22 @@ void smm_region(uintptr_t *start, size_t *size)
*size = sa_get_tseg_size();
}
+static bool is_ptt_enable(void)
+{
+ if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) ==
+ PTT_PRESENT)
+ return true;
+
+ return false;
+}
+
+/* Calculate PTT size */
+static size_t get_ptt_size(void)
+{
+ /* Allocate 4KB for PTT if enabled */
+ return is_ptt_enable() ? 4*KiB : 0;
+}
+
/* Calculate ME Stolen size */
static size_t get_imr_size(void)
{
@@ -130,6 +146,9 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base,
/* Get Tracehub size */
reserve_mem_base -= get_imr_size();
+ /* Get PTT size */
+ reserve_mem_base -= get_ptt_size();
+
/* Traditional Area Size */
reserve_mem_size = dram_base - reserve_mem_base;