diff options
| author | Saurabh Satija <saurabh.satija@intel.com> | 2016-05-03 15:15:31 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-02 03:33:52 +0200 |
| commit | e46dbcc53a10491f53a0c80c4e3c59404982b42d (patch) | |
| tree | a2ef0b396647fc93a65258bba015fa552e48c603 /src/soc/intel | |
| parent | 5b6c5a500ed416f033a22eed1d8174063ebaf143 (diff) | |
| download | coreboot-e46dbcc53a10491f53a0c80c4e3c59404982b42d.tar.xz | |
soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree
Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 3 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 00470a201a..ae9f09e51e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -332,6 +332,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->IshEnable = cfg->integrated_sensor_hub_enable; + silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; + /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0; } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index aabd42df42..fa79cf83b9 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -101,6 +101,9 @@ struct soc_intel_apollolake_config { uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ + + /* Configure LPSS S0ix Enable */ + uint8_t lpss_s0ix_enable; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ |