diff options
| author | Martin Roth <gaumless@gmail.com> | 2015-01-30 20:56:05 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2015-02-09 17:44:31 +0100 |
| commit | 2213843ae8971c2078997c5eba9e84ff3689a942 (patch) | |
| tree | bfd17b9079744abc106715a27bf80d564a022aa0 /src/soc/intel | |
| parent | ad4fa21705e66a0f350597da043c845aa79bce99 (diff) | |
| download | coreboot-2213843ae8971c2078997c5eba9e84ff3689a942.tar.xz | |
fsp_baytrail: Get FSP reserved memory from the FSP HOB list
Because the pointer to the FSP HOB list is now being saved, we can
use that to find the top of usable memory. This eliminates the need
to hardcode the size of the FSP reserved memory area.
Tested on minnowboard max for baytrail.
The HOB structure used does not seem to be present for the rangeley
or ivybridge/pantherpoint FSPs. At the very least, the GUID is not
documented in the integration guides.
Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8308
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/memmap.c | 15 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/northcluster.c | 7 |
3 files changed, 8 insertions, 16 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h index 1f4fa743b4..29309bf0a5 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -32,8 +32,6 @@ #include <fspvpd.h> #include <azalia.h> -#define FSP_RESERVE_MEMORY_SIZE 0x200000 - #define FSP_INFO_HEADER_GUID \ { \ 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 615916b96d..8a10ac80c7 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -29,18 +29,17 @@ uintptr_t smm_region_start(void) return (iosf_bunit_read(BUNIT_SMRRL) << 20); } -/* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. +/** @brief get the top of usable low memory from the FSP's HOB list + * + * The FSP's reserved memory sits just below the SMM region. The memory + * region below it is usable memory. * * The entire memory map is shown in northcluster.c + * + * @return pointer to the first byte of reserved memory */ void *cbmem_top(void) { - uintptr_t tom = smm_region_start(); - if (!tom) - tom = iosf_bunit_read(BUNIT_BMBOUND); - return (void *) tom - FSP_RESERVE_MEMORY_SIZE; + return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e5547aa..b288388db2 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -149,8 +149,7 @@ static void mc_add_dram_resources(device_t dev) uint32_t fsp_mem_base = 0; GetHighMemorySize(&highmem_size); - GetLowMemorySize(&fsp_mem_base); - + fsp_mem_base=(uint32_t)cbmem_top(); bmbound = iosf_bunit_read(BUNIT_BMBOUND); bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; @@ -162,10 +161,6 @@ static void mc_add_dram_resources(device_t dev) printk(BIOS_DEBUG, "FSP memory location: 0x%x\nFSP memory size: %dM\n", fsp_mem_base, (bsmmrrl - fsp_mem_base) >> 20); - - if ((bsmmrrl - fsp_mem_base ) != FSP_RESERVE_MEMORY_SIZE) - printk(BIOS_WARNING, "Warning: Fsp memory size does not match " - "expected memory size (%x).\n", FSP_RESERVE_MEMORY_SIZE); } printk(BIOS_INFO, "Available memory below 4GB: 0x%08x (%dM)\n", |