diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-09-28 19:54:30 +0530 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-10-09 20:10:00 +0000 |
| commit | 46caf09598575747070c599dbfd9abca9e96b831 (patch) | |
| tree | b739206d82166f6d514b70af59fd7fa953ae98ad /src/soc/intel | |
| parent | 1f33a0c799bac60b5bcc24481303ebbcdaf0e7d2 (diff) | |
| download | coreboot-46caf09598575747070c599dbfd9abca9e96b831.tar.xz | |
soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
This patch save and restore ITSS IPCx register before and after
FSP-S call.
Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/itss.h | 3 |
3 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 9d9ca01d6d..fb011833e4 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -21,19 +21,28 @@ #include <device/pci.h> #include <fsp/util.h> #include <intelblocks/chip.h> +#include <intelblocks/itss.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <soc/acpi.h> #include <soc/interrupt.h> #include <soc/irq.h> +#include <soc/itss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <string.h> void soc_init_pre_device(void *chip_info) { + /* Snapshot the current GPIO IRQ polarities. FSP is setting a + * default policy that doesn't honor boards' requirements. */ + itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* Perform silicon specific init. */ intel_silicon_init(); + + /* Restore GPIO IRQ polarities back to previous settings. */ + itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); } void soc_fsp_load(void) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 039d45a507..a2a430e695 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -29,6 +29,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/chip.h> +#include <intelblocks/itss.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <romstage_handoff.h> @@ -37,6 +38,7 @@ #include <soc/interrupt.h> #include <soc/iomap.h> #include <soc/irq.h> +#include <soc/itss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> @@ -167,8 +169,16 @@ static void pcie_override_devicetree_after_silicon_init(void) void soc_init_pre_device(void *chip_info) { + /* Snapshot the current GPIO IRQ polarities. FSP is setting a + * default policy that doesn't honor boards' requirements. */ + itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); + + /* Restore GPIO IRQ polarities back to previous settings. */ + itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* swap enabled PCI ports in device tree if needed */ pcie_override_devicetree_after_silicon_init(); } diff --git a/src/soc/intel/skylake/include/soc/itss.h b/src/soc/intel/skylake/include/soc/itss.h index 5ff9bb1e55..e6eb8b0744 100644 --- a/src/soc/intel/skylake/include/soc/itss.h +++ b/src/soc/intel/skylake/include/soc/itss.h @@ -16,6 +16,9 @@ #ifndef SOC_INTEL_SKL_ITSS_H #define SOC_INTEL_SKL_ITSS_H +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END ITSS_MAX_IRQ + #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) |